Abstract: An electronic system is packaged to provide a single etched backplane. Bus bars are physically fastened to bushings which are soldered to the backplane power etch lines to provide power to the system.Printed circuit boards are plugged into connectors mounted on the backplane for receiving power and transferring logic signals between printed circuit boards. A number of power supplies are plugged into connectors mounted on the bus bars for transmitting power, and plugged into connectors for transferring logic signals.

Abstract: A color display graphics system includes three bit map memories for storing bits representing red, green and blue colors respectively. Combinations of bits from the same address locations of each bit map memory display a pixel which could be any one of eight colors: black, blue, green, cyan, red, magenta, yellow or white. A read only memory (ROM) stores patterns made up of sixteen bits in a four-by-four matrix for each of the red, green and blue colors. The 16-bit matrices are stored in their respective bit map memories for subsequent color display. Combinations of matrices may be used to show shades of the above eight colors and the mixing of any of those shades.

Abstract: A passive signal coupler transfers data signals being transmitted over AC power lines from a first AC power distribution system to a second AC power distribution system. Each leg of the passive signal coupler coupled to a phase of the power line voltage includes a series LC circuit, tuned to the data signal carrier frequency. Each leg coupled to the first power system is terminated in a first winding of a transformer. Each leg coupled to the second power system is terminated in a second winding of the transformer.

Abstract: A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is disclosed. Also disclosed is a method and apparatus for speeding conversion of a number in binary format to decimal format by first stripping leading zeroes before the highest order non-zero bit of the binary number, and only allocating enough memory storage bits to hold the resultant decimal number. A multiplexer is used to apply a partial sum during conversion concurrently to both inputs of an adder for doubling.

Abstract: Apparatus that provides interrupt operation in a central processor based system wherein internal subsystems are operated via addresses generated by a next address generator in the processor and sent to control stores associated with each subsystem to thereby read out firmware instructions which are used by a controller in each subsystem to control the operations of same. When a special condition is detected in ones of the subsystems a trap signal is sent to the next address generator which responds by generating a microinstruction address to the subsystem that generated the trap signal. The subsystem responds to the microinstruction to read out a register, the contents of which indicate the status of processing in the subsystem including the special condition.

Abstract: A data collection terminal includes a microprocessor, a memory and a number of devices coupled to a system bus. An interrupt controller processes the device interrupt requests by sending a vector address out on the system bus to enable the microprocessor to branch to a microprogram to process the interrupt request. Apparatus is provided to receive the vector address to generate an interrupt clear signal for those interrupts which are transitory in nature. Typical examples are a document being inserted in a device or a card seated in a device.

Abstract: A microprogrammed control apparatus for dot matrix serial printers and related printing method which allows increased horizontal resolution of the printing matrix and therefore the printing quality consistent with the restriction that no printing element can be actuated before a previous energization of any printing element has been completed. The increase of the horizontal resolution is obtained by using a character description matrix with high resolution and logic circuits responsive to binary configurations read out from such matrix. In a preferred alternative, the increase of the horizontal resolution is obtained by using a "compressed" character description matrix containing a plurality of printing patterns, one for each of the columns where printing has to be performed (hereinafter "column to be printed") and a corresponding plurality of codes, each related to a printing pattern and representative of the distance/time interval between the column to be printed and the previous column to be printed.

Abstract: A data processing system includes a central processing unit (CPU), an input/output microprocessor, a main memory and a number of mass storage controllers. A block of information is transferred between one of the mass storage controllers and main memory during data multiplex control (DMC) cycles. The CPU includes registers which store the address of main memory into which the next data byte is written or read from and the range indicating the number of data bytes remaining to be transferred. Prior to a DMC cycle the CPU stores address and range information in a mailbox location in an I/O RAM and the I/O microprocessor transfers that information to channel table locations in the I/O RAM. For a DMC operation, the I/O microprocessor transfers the address and range information to the mailbox location and transfers the mass storage information to the mass storage controller. It signals a CPU interrupt and issues a read or write order to the mass storage controller.

Abstract: Data processing system architecture in which a central processing unit (CPU) and a plurality of input/output processors (I/OP), said I/OPs being connected in parallel through a bus can have access to a common working memory, under control of a memory access control unit, through a set of tridirectional gates directly connecting memory to the CPU or to the bus without interposition of registers, drivers, receivers, except said tridirectional gates, between the internal CPU channel and the memory channel. The control unit periodically monitors, in synchronism with internal CPU cycles if memory access requests from the I/OP are pending and, absent such requests, the CPU may activate memory cycles in synchronism with its internal cycles without preamble diagloue and access waiting time.

Abstract: A microprogrammed data processing system includes a central processing unit (CPU), a main memory and a number of mass storage controllers. A block of information is transferred between main memory and one of the mass storage controllers during data multiplex control (DMC) cycles. The main memory stores 2 data bytes in each word location. An input/output RAM stores channel number signals for identifying mass storage controllers. An I/O microprocessor addresses the I/O RAM to read the channel number signals onto the system bus, and a mass storage controller coupled to the system bus responds to the channel number signals to generate a read/write signal. The system responds to a request signal, the read/write signal and a signal indicative of a left or right bit of an addressed location in main memory to generate a plurality of data request signals. A read only memory is addressed in response to the data request signals to read out a plurality of microprograms for processing the data.

Abstract: Information read from a disk device includes synchronization bytes to enable a controller to get into byte synchronization with a stream of bits received from the disk. The stream of bits passes through a shift register. Firmware conditions a multiplexer which receives the parallel output of the serial register to select the high order binary ONE bit thereby enabling the controller to get into byte synchronization with the stream of bits.

Abstract: Computer control memory apparatus is disclosed wherein the microinstructions may selectively have a variable bit length. A main control memory stores microinstructions having a basic length and they are read out and stored in a microinstruction register. Microinstruction prefixes are obtained from more than one source and are selectively added to the basic length microinstruction in the microinstruction register to create longer microinstructions, as needed, for controlling the operation of the computer. The microinstruction prefixes may be obtained from a secondary control memory that is addressed at the same time as the main control memory, or may be obtained from a field of N bits which is a part of a previous microinstruction read out of the main control memory and saved in an expansion register, or may be all zeroes when it is not desired to expand a microinstruction of basic length read out of the main control memory.

Abstract: A method and apparatus for skew compensation in an optical reader is described. The method provides for calculating the amount of skew between the read scan line used to read the data and the recording path line used when the data was written on the recording media. By determining the position of each end of the scan line by counting delimiter marks along the two edges of the data being read, the skew can be calculated by determining the difference in delimiter counts. The data is divided into bands along the direction of scan within which the skew will not cause trouble misreadings at the extreme bits of the scan line within a band. The data is scanned multiple times during the transition of the data strip so that at least one good read of each data band in the data strip will occur.

Abstract: A data collection terminal includes a microprocessor, a memory and a number of devices coupled to a system bus. Included among the devices is a communication controller. An interrupt controller processes the device interrupt requests by sending out a vector address to the microprocessor. This enables the microprocessor to branch to a subroutine to process the interrupt. Apparatus is provided to enable the communication controller to generate vector addresses when it sends an interrupt request to the interrupt controller.

Abstract: A method and apparatus for a microinstruction controlled unit to recover from a read error in reading microinstructions from a control store. The method provides for the overlapping of the execution of a current microinstruction while the next microinstruction is being addressed and read from the control store. Execution of the current microinstruction is begun before it is known whether or not it was read without error. The apparatus provides for aborting the execution of the current microinstruction with the read error and the next microinstruction. During the aborted execution of the next microinstruction, the current microinstruction is reread from the control store and then executed while the next microinstruction is being reread. The execution of microinstructions is aborted in a manner that does not alter the state of the microinstruction controlled unit beyond the point that would inhibit the re-execution of the aborted microinstructions.

Abstract: The refresh logic of a dynamic MOS memory subsystem of a data processing system is tested by providing apparatus for counting refresh cycles and generating a counter output signal in a first state after a predetermined number of refresh cycles. A microprocessor periodically tests the state of the counter output signal and keeps a count of the number of times the counter output signal was tested and found to be in a second state. When the microprocessor tests and finds the counter output signal in a first state, the microprocessor compares the number of times it tested and found the counter output signal in a second state and determines if that count is within a predetermined range for correct operation.

Abstract: A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is disclosed. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. Also disclosed is apparatus utilizing a programmable memory and logic circuits that are used to subtract two operands and to generate and temporarily store a digit equal nine indication when the result of subtracting the two operands has a value of nine.

Abstract: Digital data is transmitted over AC power lines at typically a 300 baud rate and at a frequency of 130 kilohertz representing a binary ONE and 131 kilohertz representing a binary ZERO. Apparatus in the receiver relay including a quadrature detector converts the high frequency signals to digital binary signals which are applied to a microprocessor. The microprocessor generates signals to control relays in accordance with the information received from the AC power lines.