Abstract: A high speed link controller (HSLC) and a number of work stations are coupled in common to a single conductor coaxial cable. Apparatus generates data signals at high speed for transfer of information between the link controller and the work stations with reduced reflections.

Abstract: A data processing system includes a high speed link controller coupled to a number of work stations by a single coaxial conductor. Apparatus including a counter, a comparator and an adder in the high speed controller synchronizes the data bits received from the work stations to the high speed controller clocking system.

Abstract: Serial printer provided with cutter, the printer being of the type in which printing is performed by a printing head mounted on a carriage sliding on guides parallel to the printing line and a continuous printing support moves perpendicularly to the direction of such guides leaning against a substantially vertical platen. A rotating cutter is lever-mounted on the carriage over the printing head in a position very close to the printing line and it can be actuated in order to partially overlap a cutting edge of the platen, the edge being parallel to the printing line.Owing to the printing head movement along the printing line, the rotating cutter when actuated operates the transversal cutting of the continuous form. The cut form is disposed in a collecting drawer behind the platen owing to the movement imposed by the rotating cutter and to the reduced thickness of the platen which constitutes a drawer wall.

Abstract: In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus or for transferring information via a communication channel to other data processing systems during asynchronously generated information bus transfer cycles, an apparatus exists for reformatting data for transfer over the common electrical bus or via the communication channel. The apparatus is comprised of an eight-way multiplexer responsive to control bits for selecting one of eight different formats during write or read operations to or from a memory. Additionally, during read operations, the apparatus transfers a return address from a unit requesting information to the address bus so that data read from memory may be transferred to the requesting device. The formatting control bit is similarly reformatted from the data bus to the address bus bit.

Abstract: In a computer factory data collection terminal an electrical conduit enclosure for permitting wiring to be brought up through the conduit to the factory data collection terminal and for providing full wiring protection while still permitting the terminal to be installed or detached without opening the unit. A conduit enclosure having a base, cover, conduit fittings and special data and address signal connector and power connections is detachably mounted below the data collection terminal.

Abstract: A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data type field signals and a number of control signals are applied to the address terminals of a read only memory. The read only memory output signals are tested by microwords of a microprogram to branch to firmware routines to process the operand type.

Abstract: An interactive terminal includes a central processor unit (CPU) having a microprocessor and a random access memory (RAM). Signals from the microprocessor place the RAM in a write protect mode. If the RAM receives a write instruction from the microprocessor when the RAM is in the write protect mode, then an illegal condition is indicated and a nonmaskable interrupt is generated to allow the terminal to recover. When the RAM is in the write protect mode, signals from the microprocessor restore the RAM to its normal read/write mode.

Abstract: A data processing system includes a communication subsystem having an I/O microprocessor for communicating with a central processing unit and a main memory; and a line microprocessor for communicating with a number of devices. The I/O microprocessor and the line microprocessor communicate with each other through mailboxes stored in a shared memory. The line microprocessor interrupts the I/O microprocessor to process data bytes being transferred between main memory and a device requesting service when the line microprocessor has responded to the requesting device and loaded the mailbox.

Abstract: A data processing system executes a decimal multiply instruction by storing the product of a multiplier decimal digit and a multiplicand decimal digit in a read only memory and storing partial product decimal digits in a register. The units product decimal digit is read from the read only memory during one cycle and added to a partial product decimal digit. A resulting units carry is stored in a units carry flip-flop. The tens product decimal digit is read from the read only memory during another cycle and added to a higher order partial product decimal digit. A resulting tens carry is stored in a tens carry flip-flop. A multiplexer selects the output of the units carry flip-flop for adding the units carry during the next units cycle in which the next units product decimal digit is added to the higher order partial product decimal digit.

Abstract: A data processing system includes a central processing unit, a main memory, and a communication subsystem servicing a number of communication lines. The communication subsystem includes a free running timer, a line microprocessor for communicating with the communication lines and a shared memory, and an I/O microprocessor for communicating with the shared memory and the central processing unit and main memory. The line microprocessor, desiring to communicate with a specified communication line after a predetermined time delay, loads a first mailbox in shared memory with a binary number indicative of the predetermined time delay. The I/O microprocessor adds the output of the free running timer to the binary number, stores the result in a location in a random access memory, and periodically compares the result against the free running timer output. The I/O microprocessor loads a second mailbox with a control character when the results of the comparison indicate that the predetermined time delay is accomplished.

Abstract: An interactive terminal data processing system includes a number of work stations, all coupled in common to a single conductor coaxial bus which may be up to one kilometer in length. Work stations may be connected to the bus by up to a ten foot coaxial cable with the connection to the bus being typically no less than thirty feet apart.

Abstract: An address bus of a central processor unit (CPU) is tested by generating repetitive "no operation" (NO OP) instructions. A microprocessor in the CPU receives the NO OP instruction code set manually into switches and generates sequential addresses on successive CPU cycles on the address bus. The microprocessor generates a read signal during each CPU cycle which is jumpered to portions of the logic to allow continuity of operation during test.

Abstract: A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.

Abstract: A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

Abstract: A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

Abstract: A microprogrammed commercial instruction processor (CIP) is placed in a stall mode during the transfer of information between the CIP and main memory by stalling a free running clock signal. When the transfer of information is completed, the free running clock cycles. If main memory indicates an error condition, then the free running clock signal is again stalled after one cycle to allow the firmware in the CIP to process the error.

Abstract: A logical control system is provided for accommodating both single and double byte accesses to a video terminal system display memory to supply video character and visual attribute data to a video screen without limiting the quantity of visual attributes and without the needless occupation of video screen character positions by visual attribute characters.

Abstract: A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.

Abstract: A hardware monitor interface unit (HMIU) is coupled to a data processing system. Programmable hit matrices (PHM's) in the HMIU store information which is compared with information from the data processing system. The PHM's generate "hit" signals indicating comparison. These "hit" signals are received by monitors coupled to the HMIU which are used to compile the data processing system performance data. Appartus in the HMIU generates clocking signals enabling the information to be received by the HMIU and generates strobing signals to be used for timing the "hit" signals and other control signals received by the monitors.

Abstract: A data processing system includes a number of subsystems, all coupled in common to a system bus. Also coupled to the system bus is a hardware monitor interface unit (HMIU) for receiving all information transferred between subsystems. The HMIU includes programmable hit matrices (PHM's). The PHM's include memory circuits which generate "hit" signals when predetermined information addresses the memory circuits. The "hit" signals or binary ONE's are loaded into the memory circuits during a load mode during which system bus information specifically addressing the HMIU is received on two system bus cycles for each address location of the memory circuit. The data bus contains the memory circuit address during the first system bus cycle and the data during the second data bus cycle. An address bus signal identifies the cycle.