Abstract: A disk drive of a mass storage subsystem includes areas on a disk surface wherein a vendor-generated defective sector log, a software-generated defective sector log and an alternate sector log are stored. A random access memory (RAM) stores a copy of the defective sector logs. During a seek operation, firmware tests the defective sector logs in RAM to generate the alternate sector log for that cylinder number. During the read or write operation, the alternate sector log is checked before processing the sector to determine if it is a defective sector. If the sector is defective, the head is positioned to another cylinder at a head and sector address read from the alternate sector log.

Abstract: A data processing system includes a cathode ray tube (CRT) display subsystem and a floppy disk subsystem. The logic of both systems are verified by generating and transferring a fixed format stream of data bits from the CRT display subsystem to the floppy disk subsystem in modified frequency modulation (MFM) mode and checking the information received by the floppy disk subsystem against the original information presented to the CRT display subsystem.The bit rate of the data stream is varied depending on the number of address locations used in the data RAM of the CRT display subsystem to store each data bit.

Abstract: A method is disclosed for changing the horizontal and vertical resolution of an image while the image is in digitized and compressed form, where the image is first scanned and digitized to be represented as a number of discrete picture elements (pixels) and then the digitized image data is compressed. To change the resolution of an image and thereby be able to display it in smaller or larger form, the compressed image data is first analyzed and the data for certain scan lines is replicated or eliminated to respectively increase or decrease the vertical resolution of the image by a selected vertical resolution change factor. Then the compressed image data with scan lines replicated or eliminated is further processed using a selected horizontal resolution change factor to increase or decrease the horizontal resolution by respectively increasing or decreasing the number of pixels representing each scan line. The image data may also be processed so that windowing on the image may be performed.

Abstract: An optical storage card reading system using a cylindrical lens is disclosed which provides for a large viewing cone at the surface of the optical storage card thus improving the ability to read optically recorded data despite scratches or dust on the optical storage card.

Abstract: Processor apparatus is described for performing binary and decimal arithmetic operations. In performing decimal multiplication with the processor apparatus, to reduce the amount of processing to be done with the apparatus and thereby speed up the performance of the decimal multiplication, the leading zeroes prefixing the highest order significant digit in both a multiplier and a multiplicand are identified, counted and removed. Decimal multiplication is then performed using the stripped multiplier and multiplicand, and to the resultant partial product a number of zeroes are prefixed equal to the number of zeroes originally stripped from the multiplier and multiplicand. The result is the product of the original multiplier and multiplicand.

Abstract: What is disclosed is apparatus making up an arithmetic logic unit and utilizing a programmable read-only memory (PROM) to perform arithmetic functions for an associated processor. The PROM is used as a look-up table for computation results. Operands used to perform a mathematical computation make up an address to the PROM which is used to read out the computation result stored therein. Also stored in the PROM as part of each computation result are information bits indicating if the computation result is a valid answer. These bits are also read out and stored in flip-flops to indicate to the processor if the computation result is valid or invalid.

Abstract: Apparatus is provided for addressing a memory by word and by one of a number of nibbles within a word, with the ability to increment or decrement nibble and word addresses and thereby access adjacent nibbles and words without having to generate new nibble and word addresses. An initial word address is placed in an address counter and an initial nibble address is placed in a nibble control. The two addresses indicate a particular nibble within a particular word. Thereafter, only increment or decrement signals are provided to increment and decrement the nibble address and/or the word address. A nibble counter counts the increment and decrement nibble signals and when the last or first nibble in a word is addressed, an increment or decrement word address signal is respectively generated that changes the word address stored in the address counter.

Abstract: A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is described. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. Also disclosed is an arithmetic logic unit (ALU) that functions with the CPU. The ALU has operand inputs to which are connected switched steering circuits that permit particular operands and zero operands to be selectively applied to any or all of the ALU operand inputs. This allows easy performance of special arithmetic functions such as adding a decimal operand to itself when converting the decimal operand to a binary operand, and to subtract a decimal operand from zero when complementing decimal operands.

Abstract: A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main memory is controlled by a priority resolver that awards access to the main memory on the basis of predetermined priority levels assigned to CPU, I/O and refresh requests. The priority resolver produces an early signal that is usable to initiate a memory cycle before the final winner of the main memory is determined. The logic path of the lowest priority requester is the shortest path thus allowing the lowest priority requester to initiate a memory cycle in the shortest amount of time even though another requester may ultimately win use of the memory. The priority resolver also provides for the early resetting of access requests so that subsequent requests can be made with minimum delay.

Abstract: A Reader/Sorter may have an MICR read head, an OMR read head, and two OCR read heads or a combination thereof.A Reader/Sorter Adapter receives characters read by the Reader/Sorter. The characters include data and formatting symbol characters read from a document and control characters generated by the Reader/Sorter. Certain characters may be identified as queue field identifiers (QFI) by the user via software. These are usually the formatting characters. The control characters are identified as pseudo queue field identifiers (PQFI). QFI and PQFI characters are received by a Multiple Device Controller and allow the firmware to identify the length of the data fields, the head from which the characters were received, and any special conditions associated with reading of a data field.

Abstract: A data processing system having a plurality of units includes a shareable unit which is shareable between two or more of the other units. Lock apparatus is provided in the shareable unit to allow a first unit to lock the shareable unit so that no other unit attempting to lock the shareable unit will be permitted access to the shareable unit. The lock apparatus includes means that permit two units desiring to lock the shareable unit to make simultaneously asynchronous requests to lock the shareable unit. The lock apparatus further includes means to permit the unit which has locked the shareable unit to unlock the shareable unit so that it becomes available for a subsequent lock by a unit. The lock apparatus also includes means to allow the shared unit to be accessed by other units not attempting to lock the shareable unit even when the shareable unit is locked.

Abstract: A data processing system includes a cathode ray tube (CRT) display. Apparatus associated with the CRT tests and verifies the vertical and horizontal synchronization and the logic associated with a character generator. Refresh signals, horizontal synchronization signals and data bit signals from the character generator are counted. The counts of those signals which occur within a predetermined number of occurrences of vertical synchronization signals are verified.

Abstract: A track on a disk surface of a disk drive is formatted in sectors, each sector having an address portion and a data portion. The disk drive generates a byte clock signal which increments a counter. The counter output signals address a read only memory which generates signals to control the address comparison in the address portion and the reading or writing of data bytes in the data portion of the sector.

Abstract: Disclosed is a tilt-swivel base for a CRT display terminal. The base allows the CRT terminal to be readily swiveled around a vertical axis and tilted forward or backward around a horizontal axis or positioned with a combination of both movements. The cradle of the base may be placed within a recess formed in a horizontal supporting surface and thereby confine the base within the recess. By having the recess front-to-back width approximately equal to the front-to-back width of the cradle and the side to side length greater than the side to side width of the cradle, the CRT display terminal and base can be moved from side to side within the recess while still confining it to a fixed front-to-back position. By providing the cradle with a convex front surface and a triangular back surface, the base and CRT display terminal may be swiveled up to the point that one of the two angled back edges of the cradle comes into full contact with the back edge of the recess.

Abstract: A mounting bracket system mounts a factory data collection terminal vertically to a wall to secure the terminal rigidly to the wall surface and also to permit a quick disconnect of the terminal. This is accomplished by fastening two brackets with keyhole slots which are attached to the upper area of the terminal and using two spring loaded captive fasteners which are accessible from the front of the terminal and attached to the bottom of the terminal.

Abstract: In a terminal system comprising a central processor subsystem, a memory subsystem and a plurality of peripheral subsystems, all connected in common to a system bus, the system bus timing is divided into a plurality of fixed times including a central processor (CPU) bus cycle and a plurality of Direct Memory Access (DMA) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles.Particular peripheral subsystems are assigned to particular DMA channels. These DMA channels communicate with the memory subsystem on particular DMA bus cycles which are operative in a revolving priority, with the first DMA bus cycle occuring after the last DMA bus cycle of the previous sequence of DMA bus cycles.A plurality of peripheral subsystems are wired to a particular DMA channel in a daisy chain fashion with the peripheral subsystem wired closest to the system bus having top priority.

Abstract: A track of a disk device is formatted on a single revolution of the disk by using a read only memory (ROM) to store control codes and a random access memory (RAM) to store address field and data field bytes. A DMA controller simultaneously addresses ROM and RAM. Control codes are read into a control first in-first out memory and data codes are read into a data first in-first out memory. The control codes are applied to a decoder whose output signals control cyclic redundancy check and error detection and correction logic as well as the data first in-first out memory. The serial output from both the data first in-first out memory and the cyclic redundancy check logic are written on disk track.

Abstract: A hardware monitoring interface unit (HMIU) is coupled to a data processing unit and receives all information transferred between subsystems of the data processing unit. Programmable hit matrices (PHM's) include input latches for receiving the information, memory circuits for storing binary ONE's in locations addressed by predetermined portions of the information and output latches for storing the binary ONE's or "hit" signals read from the memory circuits. The "hit" signals are plug-wired into logic circuits and counters in a monitor to collect statistical data.

Abstract: An error detection system is disclosed for not only indicating but eliminating certain errors which may occur during the transfer of information between communication busses in a data processing system wherein plural communication busses each provide a common information path to plural data processing units including memory units, peripheral control units, central processing units and ISL units, and wherein each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs. The error detection system requires no special supporting software or firmware on the part of any data processing unit on any of the communication busses.

Abstract: An interactive terminal system includes a high speed link controller (HSLC) and a number of work stations, all coupled in common to a single conductor coaxial bus. The HSLC includes apparatus controlled by a microprocessor to put the HSLC in a wraparound test mode. The microprocessor transfers test bytes which pass through the HSLC logic and are checked by the microprocessor.