Patents Represented by Attorney George O. Saile
  • Patent number: 7153766
    Abstract: A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: December 26, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Beichao Zhang, Wuping Liu, Liang-Choo Hsia
  • Patent number: 7130297
    Abstract: In the present invention a voice and data network is disclosed that has applicability to a home or building where existing phone lines are used to interconnect multiple phones and computers within the network. Voice and data modules connect telephones and computers to the existing telephone wiring in a home or building. A link to wide area network allows phone calls to be placed between the network and the Public Service telephone network. All devices connected to the telephone wiring have their own ID and communicate by Tokens in Ethernet technology. This allows Ethernet packets to perform a plurality of communications between a plurality of devices connected to the network under the control of tokens. The communications is accomplished by passing packets containing voice and data signals between phones and computers internal to the network and to an external port to connect to outside of the network.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: October 31, 2006
    Inventor: Peter C. P. Sun
  • Patent number: 7064538
    Abstract: A system and methods for an interface for magnetic sensors to determine a rotational angle has been achieved. This interface can be used for magnetic sensors providing analog signals of the sine and cosine values of the angle to be determined. Analog signals are being processed in two measurement paths for the sine and cosine signal each until the desired angle is computed by a CORDIC processor. The first stage of the measurement path is the conversion of the sine and cosine signals from analog to digital by 2nd order delta-sigma modulators with an over-sampling ratio. A low-pass decimation filter with sinc3 characteristic performs the digital value computation. The next stage normalizes the digitized sine and cosine values to correct offset and scaling deviations.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: June 20, 2006
    Assignee: Dialog Semiconductor GmbH
    Inventor: Juergen Kernhof
  • Patent number: 7061730
    Abstract: A spin-valve magnetoresistive read element has a thin conductive lead layer of high sheet conductivity, high hardness, high melting point, high corrosion resistance and lacking the propensity for smearing, oozing, electromigration and nodule formation. Said lead layer is formed upon the hard magnetic longitudinal bias layer of an abutted junction spin-valve type magnetoresistive read head and said read head is therefore suitable for reading high density recorded disks at high RPM.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: June 13, 2006
    Assignee: Headway Technologies, Inc.
    Inventors: Cheng T. Horng, Mao-Min Chen, Chen-Jung Chien, Cherng-Chyi Han, Chyu-Jiuh Torng, Ru-Ying Tong
  • Patent number: 7061339
    Abstract: Methods to achieve low power consumption, high output amplitude and an improved high frequency stability, and high speed for voltage-controlled oscillators are disclosed These methods includes to provide a current mirror, a power supply voltage Vdd, two single-ended outputs, a lower layer of gain providing structure comprising cross-coupled transistors, an upper layer of gain providing structure, a control voltage, a pair of capacitors to block a DC-connection to the gates of said cross-coupled transistors, a pair of resistors, and an LC-tank. Important steps of these methods include to set the time instances when said transistors of lower layer of gain providing structure open and close, to shut-down the transistors of lower layer of gain providing structure as soon as the energy required to keep the oscillations in said LC-tank is secured, to add additional gain in the amplification loop; and to pump-out charges of the channels of said transistors of said lower layer gain providing structure.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: June 13, 2006
    Assignee: Dialog Semiconductor GmbH
    Inventors: Andreas Sibrai, Nikolay Tchamov
  • Patent number: 7050273
    Abstract: A method for fabricating a longitudinally hard biased, bottom spin valve GMR sensor with a lead overlay (LOL) conducting lead configuration and a narrow effective trackwidth. The advantageous properties of the sensor are obtained by providing two novel barrier layers, one of which prevents oxidation of and Au diffusion into the free layer during annealing and etching and the other of which prevents oxidation of the capping layer during annealing so as to allow good electrical contact between the lead and the sensor stack.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: May 23, 2006
    Assignee: Headway Technologies, Inc.
    Inventors: Cheng T. Horng, Mao-Min Chen, Chen-Jung Chien, Cherng-Chyi Han, Ru-Ying Tong, Chyu-Jiuh Torng, Hui-Chuan Wang
  • Patent number: 7046556
    Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: May 16, 2006
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Kimihiro Satoh, Tomoya Saito
  • Patent number: 7045901
    Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: May 16, 2006
    Assignee: Megic Corporation
    Inventors: Mou-Shiung Lin, Bryan Peng
  • Patent number: 7045841
    Abstract: An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) has a tunneling barrier layer of substantially uniform and homogeneous Al2O3 stoichiometry. The barrier layer is formed by depositing Al on a CoFe layer or a CoFeā€”NiFe bilayer having an oxygen surfactant layer formed thereon, then oxidizing the Al by radical oxidation. The underlying surfactant layer contributes oxygen to the bottom surface of the Al, forming an initial amorphous Al2O3 layer. This layer produces small, uniform grains in the remaining Al layer, which promotes a uniform oxidation of the Al between its upper and lower surfaces by the subsequent radical oxidation. A final annealing process to set a pinned layer magnetization enhances the homogeneous oxidation of the layer.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: May 16, 2006
    Assignees: Headway Technologies, Inc., Applied Spintronics, Inc.
    Inventors: Cheng T. Hong, Ru-Ying Tong
  • Patent number: 7046999
    Abstract: A wireless communication system that transmits content signals and remote control signals between a content retention and distribution system and a content reproduction terminal over a half-duplex channel such as an RF channel having the same frequency band. The wireless communication system includes a base station and a remote station. The base station formats and transmits the content signal over the half-duplex channel. The remote station receives the transmitted content signal and transfers the content signal to the content reproduction terminal. The content reproduction terminal has an input device to create remote control signals for the content retention and distribution system. The remote station receives the remote control signals from the content reproduction terminal and transmits the remote control signal to the base station for transfer to the content retention and distribution system on the half-duplex channel.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: May 16, 2006
    Assignee: Nasaco Electronics (Hong Kong) Ltd.
    Inventors: Ka Ming Wu, Yan Kwan So
  • Patent number: 7042682
    Abstract: Conventional perpendicular writers that utilize an extended return pole are subject to large flux leakage. This problem has been reduced in the prior art by adding a downstream shield. This still leaves significant upstream leakage. This has now been eliminated by adding an upstream shield and then connecting the up and downstream shields by using side shields. The latter need not extend all the way from the downstream to the upstream shield in which case their thickness is increased relative to the full side shields.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: May 9, 2006
    Assignee: Headway Technologies, Inc.
    Inventors: Hung Liang Hu, Yaw Shing Tang, Liji Guan, Kochan Ju
  • Patent number: 7038880
    Abstract: An inductive-type write head and its method of fabrication are disclosed. The write head has a vertically separated two-element planar coil of reduced resistance which is the result of forming the lower of the two coils with windings of a greater height and substantially larger cross-sectional area than those of the upper coil. The formation of a lower coil with greater height is possible because of a surface planarization that allows separating the coils by an alumina layer of minimal thickness. This method allows the reduction of coil resistance without the necessity of enlarging the head dimensions. The reduced resistance results in lower power consumption and the elimination of pole tip protrusion caused by excessive heating during operation.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: May 2, 2006
    Assignee: Headway Technologies, Inc.
    Inventors: Cherng-Chyi Han, Danning Yang, Mao-Min Chen
  • Patent number: 7038550
    Abstract: A circuit and a method are given, to realize and implement an oscillator circuit with a Smart Current Controlled (SCC) Resonator Driver. A newly introduced controlled current source for a crystal oscillator's amplifier element produces a controlled driving current for the resonator element during operation in both phases of the oscillation cycle to reach for low phase noise and reduced power consumption of the circuit. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with modern integrated circuit technologies.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: May 2, 2006
    Assignee: Dialog Semiconductor GmbH
    Inventor: Antonello Arigliano
  • Patent number: 7039784
    Abstract: A method and apparatus for dynamically balancing the loading of video data storage devices facilitates the transfer of video data by acquiring a listing of locations and loading of all segments of a requested video data. Those storage devices containing copies of each segment of the video data having a least loading are selected. If the loading of the storage devices exceed their maximum capacity, the segment is divided into sub-segments and stored to storage devices with minimum loading. The presence of all segments of the requested video data is determined. If there are missing segments of the requested video data, each of those missing segments is assigned a file identification and file location, such that those missing segments are retrieved from a back-up storage device and assigned to data storage devices having the least loading for transfer to a requesting computer system.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: May 2, 2006
    Assignee: Info Value Computing Inc.
    Inventors: Monsong Chen, Dah-Weih Duan, Aparna Pappu, Bodhi Mukherjee
  • Patent number: 7034873
    Abstract: Effectively defect free images are obtained from CMOS image sensors through a two step method in which the addresses of bad pixels are recorded during sensor testing and stored in an on-chip directory. Then, during sensor readout, each pixel address is checked to determine if it represents that of a bad pixel. If this is determined to be the case, the bad pixel value is replaced by another value. This replacement value is generated from an average of the nearest-neighbors that are not defective. If testing is performed at the wafer level, said bad pixel and nearest neighbor data may be used to modify the final level wiring so that bad pixels are disconnected and replaced by their nearest neighbors.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: April 25, 2006
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Sunetra K. Mendis, Tzi-Hsiung Shu
  • Patent number: 7035060
    Abstract: A problem associated with current bottom spin valve designs is that it is difficult to avoid magnetic charge accumulation at the edge of the sensor area, making a coherent spin rotation during sensing difficult to achieve. This problem has been eliminated by introducing an exchange coupling layer between the free layer and the ferromagnetic layer that is used to achieve longitudinal bias for stabilization and by extending the free layer well beyond the sensor area. After all layers have been deposited, the read gap is formed by etching down as far as this layer. Since it is not critical exactly how much of the biasing layers (antiferromagnetic as well as ferromagnetic) are removed, the etching requirements are greatly relaxed. Whatever material remains in the gap is then oxidized thereby providing a capping layer as well as a good interface for specular reflection in the sensor region.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: April 25, 2006
    Assignee: Headway Technologies, Inc.
    Inventors: Yun-Fei Li, Hui-Chuan Wang, Chyu-Jiuh Torng, Cherng-Chyi Han
  • Patent number: 7031192
    Abstract: A data control unit is used to proved program, erase and verify signals to a non-volatile metal-oxide3-nitride-oxide-semiconductor (MONOS) memory. The data control unit comprises a plurality of sub-units that each contains a sense amplifier, two bi-directional flip-flop latches coupled in series and a program, erase and verify circuit. The two flip-flop latches each perform a task as a master latch or a slave latch depending on the memory operation. The program, erase and verify circuit in each sub-unit are connected together in a serial fashion such that multiple verification results are accumulated into one final result. Control signals are exchanged between a chip control unit and the data control unit to perform specified memory operations.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: April 18, 2006
    Assignee: Halo LSI, Inc.
    Inventors: Ki-Tae Park, Tomoko Ogura
  • Patent number: 7029375
    Abstract: The retaining ring has a plurality of slurry channels wherein each alternate channel is recessed away from the inner circumference of the pad contacting surface forming a recess which extends upward from the bottom surface sufficient to prevent contact of the retaining ring with the polishing pad. Each recess curves towards the inner circumference of the retaining ring in a manner to form a rounded tab, tangent to the inner circumference of the retaining ring, and meeting the inner circumference at the exit end of an adjacent non-recessed slurry channel. The total effective contact length of the ring with the wafer edge is about one-tenth of the wafer perimeter. This is sufficient to properly contain the wafer during polishing and provides a large area of undistorted polishing pad at the wafer edge. By adjusting the operating pressure of the polishing head, it is possible to obtain polishing rates at the wafer edge which are larger or smaller than the overall wafer polishing rate.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: April 18, 2006
    Assignee: Tech Semiconductor Pte. Ltd.
    Inventors: Yew Hoong Phang, Jianguang Chang
  • Patent number: 7022383
    Abstract: Although it is known that exchange bias can be utilized in abutted junctions for longitudinal stabilization, a relatively large moment is needed to pin down the sensor edges effectively. Due to the inverse dependence of the exchange bias on the magnetic layer thickness, a large exchange bias has been difficult to achieve by the prior art. This problem has been solved by introducing a structure in which the magnetic moment of the bias layer has been approximately doubled by pinning it from both above and below through exchange with antiferromagnetic layers. Additionally, since the antiferromagnetic layer is in direct abutted contact with the free layer, it acts directly to help stabilize the sensor edge, which is an advantage over the traditional magnetostatic pinning that had been used.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: April 4, 2006
    Assignee: Headway Technologies, Inc.
    Inventors: Yun-Fei Li, Hui-Chuan Wang, Chyu-Jiuh Torng, Cherng-Chyi Han, Mao-Min Chen
  • Patent number: 7022625
    Abstract: A method of forming a silicon nitride-silicon dioxide, composite gate dielectric layer, offering reduced risk of boron penetration from an overlying boron doped polysilicon gate structure, has been developed. A porous, silicon rich silicon nitride layer is first deposited on a semiconductor substrate, allowing a subsequent thermal oxidation procedure to grow a thin silicon dioxide layer on the semiconductor substrate, underlying the porous, silicon rich silicon nitride layer. A two step anneal procedure is then employed with a first step performed in a nitrogen containing ambient to densify the porous, silicon rich silicon nitride layer, while a second step of the anneal procedure, performed in an inert ambient at a high temperature, reduces the foxed charge at the silicon dioxide-semiconductor interface.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: April 4, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chew Hoe Ang, Alan Lek, Wenhe Lin