Abstract: A new method of silane abatement is achieved. The novel silane abatement system comprises a water-filled chamber within an outer chamber. An air intake is located in one upper portion of said outer chamber and an exhaust output is located in another upper portion of the outer chamber. A silane gas intake pipe runs into the outer chamber and has its output under water in the water-filled chamber. A drain is connected through a valve at a bottom portion of the water-filled chamber. Many safety features are built into the wet abatement system, including temperature and water level sensors, water sprinklers, and means for shutting off air supply, exhaust, and silane intake. Waste silane gas is bubbled into a water-filled chamber. The waste silane gas is reacted with oxygen in water in the water-filled chamber whereby SiO2 precipitates are formed and wherein the SiO2 precipitates settle to a bottom surface of the water-filled chamber.

Abstract: Electrical connector housings are formed of a conductive loaded resin-based material which provides superior protection from EMI and RFI by absorbing such interfering signals. The conductive loaded resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination thereof, in a base resin host. The percentage by weight of the conductive powder(s), conductive fiber(s), or a combination thereof is between about 20% and 40% of the weight of the conductive loaded resin-based material. The micron conductive powders are formed from non-metals, such as carbon, graphite, that may also be metallic plated, or the like, or from metals such as stainless steel, nickel, copper, silver, that may also be metallic plated, or the like, or from a combination of non-metal, plated, or in combination with, metal powders. The micron conductor fibers preferably are of nickel plated carbon fiber, stainless steel fiber, copper fiber, silver fiber, or the like.

Abstract: A method for integrating a SONOS device with an improved top oxide with SiO2 gate oxides of different thickness is described. In a first embodiment during ISSG oxidation to form the SiO2 gate oxides, a thin sacrificial silicon nitride layer is used over the top oxide of the ONO to minimize loss and to control the top oxide thickness. In a second embodiment the top oxide layer for the SONOS device is formed by depositing an NO stack. During ISSG oxidation to form the SiO2 gate oxides a portion of the Si3N4 in the NO stack is converted to SiO2 to form the top oxide with improved thickness control.

Abstract: Low cost antennas and electromagnetic absorbing parts formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises conductive fibers, conductive powders, or in combination thereof in a resin base host wherein the ratio of the weight of the conductor fibers, conductor powders, or combination of conductor fibers and conductor powders to the weight of the base resin host is between about 0.20 and 0.40. The conductive fibers or conductive powders can be stainless steel, nickel, copper, silver, carbon, graphite, plated fibers or particles, or the like. The antenna elements can be formed using methods such as injection molding or extrusion. Virtually any antenna, ground planes, or shielding packages fabricated by conventional means of metal can be fabricated using the conductive loaded resin-based materials.

Abstract: To form a spin valve device, start by forming a gap layer. Form a buffer layer with a layer of refractory material on the buffer layer. Form patterned underlayers including a magnetic material for providing trackwidth and longitudinal bias on the buffer layer comprising either a lower antiferromagnetic layer stacked with a ferromagnetic layer or a Cr layer stacked with a permanent magnetic layer. Form an inwardly tapered depression in the patterned underlayers down to the buffer layer by either ion milling through a mask or a stencil lift off technique. Form layers covering the patterned underlayers that cover the inwardly tapered depression. Form free, pinned, spacer and antiferromagnetic layers. Form conductors either on a surface of the antiferromagnetic layer aside from the depression or between the buffer layer and the patterned underlayers.

Abstract: This invention provides a method and apparatus for displaying an unscaled image frame on an LCD panel. The method and apparatus uses the same line buffers available to the digital signal processor DSP formerly used for scaling the displayed image up or down in size. No extra frame buffers are required by this invention since the frame rates of the source image and the LCD panel are the same. The image frame buffer is written to the LCD panel on every other panel vertical synchronization pulse. The vertical synchronization timing is shifted to the left or right in the time domain to center the image on the LCD panel.

Abstract: A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test system is initialized to a strobe set point relative to a system clock cycle. Next, the function of each of the circuits is partially tested, in parallel, using the strobe set point. Next, the circuit yield of the circuit group from the step of partially testing at the strobe set point is logged. Next, the data strobe is updated to a new strobe set point. Next, the steps of testing, logging, and updating are repeated until a specified range of strobe set points is completed. Finally, the data strobe is set for the circuit group to the strobe set point associated with the highest circuit yield.

Abstract: A magnetic tunneling junction (MTJ) memory cell for a magnetic random access memory (MRAM) array is formed as a chain of magnetostatically coupled segments. The segments can be circular, elliptical, lozenge shaped or shaped in other geometrical forms. Unlike the isolated cells of typical MTJ designs which exhibit curling of the magnetization at the cell ends and uncompensated pole structures, the present multi-segmented design, with the segments being magnetostatically coupled, undergoes magnetization switching at controlled nucleation sites by the fanning mode. As a result, the multi-segmented cells of the present invention are not subject to variations in switching fields due to shape irregularities and structural defects.

Abstract: An improved read-write head for use with magnetic disks is described. This improvement has been achieved by providing the read head with shields that are limited to performing only shielding and do not share other magnetic functions with parts of the write head. This allows the write pole to be located very close to the read head since the top shield is no longer required to provide a flux return path, this function now being provided by a separate return flux pole. The separation between the read and write heads is now limited only by the need to achieve an optimum vertical field profile. Two key advantages of this structure are a substantial reduction in the jagging distance of the system and a reduced interference field from the write flux.

Abstract: An integrated circuit module has a common function known good integrated circuit die with selectable functions. The selectable functions are selected during packaging of the known good integrated circuit die. The known good integrated circuit die is mounted to a second level substrate. The second level substrate has wiring connections to the input/output pads of the known good integrated circuit die that select desired input functions and output functions. Further, the wiring connections on the second level substrate provide signal paths to transfer signals to the desired input function and signals from the desired output function, and signals to and from the common functions. Also, the wiring connections form connections between the input/output pads and external circuitry. To select the desired input functions and the desired output functions, appropriate logic states are applied to input/output pads connected to a function selector to configure a functional operation of the integrated circuit module.

Abstract: The domino asynchronous successive approximation (ASA) analog-to-digital converter (ADC) converts an analog signal to an n-bits digital signal. The domino ASA ADC is made out of n-blocks, corresponding to the number of n-bits of the digital output. Each of these n-blocks generates a conversion bit and calibrates all following blocks, comparable to a domino structure. One key advantage of the domino ASA ADC is its modular structure; each block is independent from all others. The unity capacitors used need to be matched only within their specific blocks. The architecture is very flexible; it is possible to increase the resolution by adding more blocks of the same kind. The ASA ADC is very fast, its speed is only limited the RC constants during the sampling and measurement phase and the speed of the comparators used.

Abstract: A low cost moldable transformer or trans-inductor core, referred to in this description as a transductor. Elements of the transductor core are formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises micron conductor fibers, micron conductor powders, or in combination thereof homogenized within a base resin host wherein the ratio of the weight of the conductor fibers, conductor powders, or combination thereof to the weight of the base resin host can be between about 0.20 and 0.40. The micron conductive fibers or powders, can be of stainless steel, nickel, copper, silver, carbon, graphite, plated particles, plated fibers, or the like. Transductors can be formed using methods such as injection molding, over-molding, thermo-set, protrusion, extrusion, compression, or the like, in combination with a large number of production or wire wrapping techniques to achieve desired electrical characteristics.

Abstract: A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.

Abstract: In a translinear amplifier, where the output voltage difference is kept at the same relative difference as the input voltage difference and which is normally formed by two current balancing circuits and some form of an amplifier stage, said amplifier stage is drastically simplified and even replaced by a simple diode. Two additional functions sharply limit the analog operating region: an added current limiting transistor on one side and the purpose use of the voltage limited by the power supply on the other side. One key objective is linearly switching on or off a transistor, and getting sharp maxima and minima of its RDSon at the extreme ends.

Abstract: Heat dissipation during the operation of integrated circuit chips is an old problem that continues to get worse. The present invention significantly ameliorates this by placing an embedded heat pipe directly beneath the chip. Using powder injection molding, the lower portion of the package is formed first as an initial green part which includes one or more cavities. The latter are then lined with a feedstock that is designed to produce a porous material after sintering, at which time a working fluid is introduced into the porous cavities and sealed, thereby forming one or more heat pipes located directly below the chip. The latter is then sealed inside an enclosure. During operation, heat generated by the chip is efficiently transferred to points outside the enclosure. A process for manufacturing the structure is also described.

Abstract: A process for integrating the fabrication of double diffused drain (DDD) MOSFET devices with the fabrication sub-micron CMOS devices, has been developed. The process features formation of an insulator hard mask shape on an underlying polysilicon gate structure shape in the DDD MOSFET region, while only a polysilicon gate structure shape is formed in the CMOS device region. High energy ion implantation procedures are employed to form the deep source/drain regions of the DDD MOSFET devices with the insulator hard mask shape preventing the high energy implantation procedure from disturbing the underlying channel region. An anneal procedure used activate and drive—in the implanted ions in the deep source/drain region of the DDD MOSFET device is followed by formation of the shallower source/drain regions of the sub-micron CMOS devices.

Abstract: A test pattern generation and comparison circuit creates test pattern stimulus signals for and evaluates response signals from logic or memory such as random access memory (RAM). It utilizes both parallel and serial interfaces to the logic/memory under test. The test pattern generation and comparison circuit further provides a method for testing logic and memory utilizing built-in self test (BIST) techniques. The method uses a programmable logic/memory commands which are translated into physical logic signals and timings for the logic or memory under test. The results of the test pattern generated and applied to the logic or memory are compared to expected results. The result of the comparison is a pass/fail designation. In addition, the comparison of the expected test results with the actual test results provides information on the exact location of the failure.

Abstract: A method for forming small, isolated device structures by photolithography, utilizing overlapping bi-layer suspension-bridge shaped photomasks. The use of a suspended mask to define a device shape beneath it eliminates the problems associated with uneven undercutting of the usual bi-layer mask which is a stencil portion formed on a lower pedestal. In particular, the use of a suspended mask eliminates undesirable dielectric buildup around the device caused by an insufficiently undercut pedestal or of premature mask lift-off caused by an overly undercut pedestal.

Abstract: A method of fabricating a magnetic read/write head and slider assembly, wherein the assembly has improved heat spreading and dissipation properties and the read/write head exhibits significantly reduced thermal protrusion during operation. The method of fabrication is simple and efficient, involving only the extension of at least one of the conductive mounting pads so that it is in thermal contact with a portion of the slider surface that is directly above the read/write element.

Abstract: This invention teaches a way for the shield to shield (S1-S2) distance of a magnetic read head to be reduced. The key feature is that the upper and lower dielectric layers D1 and D3, which are normally pure aluminum oxide, have each been replaced by a bilayer dielectric, which consists of aluminum oxide in contact with the shield layer followed by a layer of a high voltage breakdown material. For D1 this layer may be either tantalum oxide or tantalum nitride while for D3 our preferred material has been tantalum oxide. The addition of the two high breakdown layers allows the thickness of the upper and lower dielectric layers to be reduced without having to reduce the S2—S2 voltage difference.