Abstract: An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) has a tunneling barrier layer of substantially uniform and homogeneous Al2O3 stoichiometry. The barrier layer is formed by depositing Al on a CoFe layer or a CoFe—NiFe bilayer having an oxygen surfactant layer formed thereon, then oxidizing the Al by radical oxidation. The underlying surfactant layer contributes oxygen to the bottom surface of the Al, forming an initial amorphous Al2O3 layer. This layer produces small, uniform grains in the remaining Al layer, which promotes a uniform oxidation of the Al between its upper and lower surfaces by the subsequent radical oxidation. A final annealing process to set a pinned layer magnetization enhances the homogeneous oxidation of the layer.

Abstract: A method for forming top and bottom spin valve sensors and the sensors so formed, the sensors having a strongly coupled SyAP pinned layer and an ultra-thin antiferromagnetic pinning layer. The two strongly coupled ferromagnetic layers comprising the SyAP pinned layer in the top valve configuration are separated by a Ru spacer layer approximately 3 angstroms thick, while the two layers in the bottom spin valve configuration are separated by a Rh spacer layer approximately 5 angstroms thick. This allows the use of an ultra thin MnPt antiferromagnetic pinning layer of thickness between approximately 80 and approximately 150 angstroms. The sensor structure produced thereby is suitable for high density applications.

Abstract: Circuits and methods to design and to fabricate said circuits to accomplish a two-level DRAM cell or a multilevel DRAM cell using a natural transistor have been achieved. The usage of a natural transistor, having a threshold voltage of close to zero, as a pass transistor reduces the amount of current required for a read operation significantly. The usage of a natural transistor in a multi-level DRAM is enabling to implement easily a high number of voltage levels, and thus more information, in one DRAM cell and is reducing the amount of output current required as well. The fabrication of said DRAM cells in an integrated circuit, comprising a natural transistor and standard transistors, include masking of the natural transistor during the ion implantation to avoid impurities increasing the threshold voltage.

Abstract: A system and methods to convert a digital bit stream to analog values without previous knowledge of the sample rate of the incoming digital bit stream has been achieved. The system comprises a sample rate measurement device being able to measure the sample rate out of the incoming digital bit stream. Another device is removing all bits, which are not required for the digital to analog conversion from the incoming bit stream. The measured and calculated sample rate is added to the “cleaned” bit stream and a digital to analog conversion device is performing the conversion using the sample rate which has been added to the bit stream.

Abstract: A method for forming MRAM cell structures wherein the topography of the cell is substantially flat and the distance between a bit line and a magnetic free layer, a word line and a magnetic free layer or a word line and a bit line and a magnetic free layer is precise and well controlled. The method includes the formation of an MTJ film stack over which is formed both a capping and sacrificial layer. The stack is patterned by conventional means, then is covered by a layer of insulation which is thinned by CMP to expose a remaining portion of the sacrificial layer. The remaining portion of the sacrificial layer can be precisely removed by an etching process, leaving only the well dimensioned capping layer to separate the bit line from the magnetic free layer and the capping layer. The bit line and an intervening layer of insulation separate the free layer from a word line in an equally precise and controlled manner.

Abstract: A process sequence used to integrate an anneal cycle, used to activate ion implanted dopants in a polysilicon gate structure, and the definition of offset silicon oxide spacers on the sides of the polysilicon gate structure, has been developed. The process sequence features ion implantation of dopants into a blanket polysilicon layer located overlying a metal oxide semiconductor field effect transistor (MOSFET), gate insulator layer. After definition of the polysilicon gate structure a silicon oxide layer is deposited, followed by an anneal procedure allowing activation of the implanted dopants in the polysilicon gate structure to occur. Out diffusion of implanted dopants during the activation anneal procedure is minimized as a result of the overlying silicon oxide layer. An anisotropic dry etching procedure is then performed on the silicon oxide layer resulting in the definition of offset silicon oxide spacers on the sides of the polysilicon gate structure.

Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

Abstract: The current mirror configuration includes four branches, a biasing branch, a first comparator branch, a second comparator branch and a measurement branch. The measurement branch is connected to a pad of the IC device and a measurement current is charged on to the pad. The measurement current is mirrored from the current of the biasing branch and the measurement current is mirrored to the second comparator branch. The biasing branch is mirrored to the first comparator branch using a scale that the current of the first comparator branch is smaller than the current of the biasing branch. In case of a short-circuit, the current of the measurement branch is larger than the current of the first comparator branch.

Abstract: A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks.

Abstract: The present invention is related to methods and systems for detecting defective imaging array pixels and providing correction, thereby reducing or eliminating visible image artifacts. One embodiment of the present invention provides an on-line bad pixel detection and correction process that compares a first pixel readout value with a first value related to the readout values of other pixels in first pixel's local neighborhood. When the first pixel readout value varies by more than a first amount as compared with the first value, a second value related to the readout values of the neighboring pixels is used in place of the first pixel readout value.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.

Abstract: Devices with embedded silicon or germanium nanocrystals, fabricated using ion implantation, exhibit superior data-retention characteristics relative to conventional floating-gate devices. However, the prior art use of ion implantation for their manufacture introduces several problems. These have been overcome by initial use of rapid thermal oxidation to grow a high quality layer of thin tunnel oxide. Chemical vapor deposition is then used to deposit a germanium doped oxide layer. A capping oxide is then deposited following which the structure is rapid thermally annealed to synthesize the germanium nanocrystals.

Abstract: A high performance specular free layer bottom spin valve is disclosed. This structure made up the following layers: NiCr/MnPt/CoFe/Ru/CoFe/Cu/free layer/Cu/Ta or TaO/Al2O3. A key feature is that the free layer is made of a very thin CoFe/NiFe composite layer. Experimental data confirming the effectiveness of this structure is provided, together with a method for manufacturing it and, additionally, its longitudinal bias leads.

Abstract: A data storage device (10) includes a stator (20), a rotor (50) rotatable about the stator via a pair of bearings (26), a cover (70), and two data storage disks (80). The stator includes a baseplate (22), and radially extending stator laminations (32) under the baseplate. The bearings are fixed in top and bottom ends of the baseplate. The rotor includes a spindle shaft (52), a hub (54), and a drive member (56). The shaft is fixed in the bearings, and the hub is fixed to a top end of the shaft. The drive member is fixed to a bottom end of the shaft, at a side of the baseplate opposite from the hub. The cover is fixed to a bottom of the baseplate, surrounding the drive member. The cover helps prevent contaminants such as dust from entering a clean chamber of the data storage device that surrounds the shaft.

Abstract: A method for forming a trimmed upper pole piece for a magnetic write head, said pole piece having a tapered profile that is widest at its trailing edge. Such a pole piece is capable of writing narrow tracks with sharply and well defined patterns and minimal overwriting of adjacent tracks. The present method produces the necessary taper by using NiCr, NiFeCr, Rh or Ru as write gap filling materials which have an etch rate which is substantially equal to the etch rate of the other layers forming the pole piece and are highly corrosion resistant. As a result, the write gap does not protrude to mask the effects of the ion-beam etch used to form the taper.

Abstract: An MTJ (magnetic tunneling junction) device particularly suitable for use as an MRAM (magnetic random access memory) or a tunneling magnetoresistive (TMR) read sensor, is formed on a seed layer which allows the tunneling barrier layer to be ultra-thin, smooth, and to have a high breakdown voltage. The seed layer is a layer of NiCr which is formed on a sputter-etched layer of Ta. The tunneling barrier layer for the MRAM is formed from a thin layer of Al which is radically oxidized (ROX), in-situ, to form the layer with characteristics described above. The tunneling barrier layer for the read sensor formed from a thin layer of Al or a HfAl bilayer which is naturally oxidized (NOX), in situ, to form the barrier layer. The resulting device has generally improved performance characteristics in terms of GMR ratio and junction resistance.

Abstract: Reduction of the free layer thickness in GMR devices is desirable in order to meet higher signal requirements, besides improving the GMR ratio itself. However, thinning of the free layer reduces the GMR ratio and leads to poor thermal stability. This problem has been overcome by making AP2 from an inverse GMR material and by changing the free layer from a single uniform layer to a ferromagnetic layer AFM (antiferromagnetically) coupled to a layer of inverse GMR material. Examples of alloys that may be used for the inverse GMR materials include FeCr, NiFeCr, NiCr, CoCr, CoFeCr, and CoFeV. Additionally, the ruthenium layer normally used to effect antiferromagnetic coupling can be replaced by a layer of chromium. A process to manufacture the structure is also described.

Abstract: This invention provides a circuit and a method for interfacing a subscriber information module, SIM to a base band controller for a mobile phone. It provides voltage level shifting to allow a low voltage base band controller chip to interface to a higher voltage SIM card. The higher voltage bus goes to the SIM card of a mobile phone. The subscriber information module typically contains personal information such as telephone number, identification codes and pin numbers. The circuit of this invention uses active transistor pull-down and pull-up mechanisms. The active pull-up is active for less than one bit time so that the SIM card sees only a 20 kilo ohm resistor allowing performances equal to or better than ISO7816 specifications.

Abstract: A circuit and method are given, which realizes a stable yet sensitive differential capacitance measuring device with good RF-suppression and with very acceptable noise features for use in capacitive sensor evaluation systems. By evaluating the difference of capacitor values only—with the help of a switched capacitor front-end—large spreads of transducer capacitor values are tolerable. Furthermore a mode of operation can be set up, where no essential galvanic connection between sensor input and the active read-out input at any given time is existing. The solution found exhibits a highly symmetrical construction. Using the intrinsic advantages of that solution the circuit of the invention is manufactured as an integrated circuit with standard CMOS technology at low cost.