Abstract: A method for designing and fabricating an integrated circuit is disclosed. Signal line interconnect widths are determined by performing an electromigration analysis on a trial layout of the integrated circuit. A representative circuit for an integrated circuit is designed and a trial layout is created that includes a plurality of nets. A preprocessor 505 eliminates nets that do not need further validation. An extraction process 510 generates an RC network representation of each remaining net that is to be validated to form a distributed load simulation model. Distributed capacitance and resistance of signal lines is included with load capacitance of receivers to provide an accurate profile of current flow. A profile of current flowing in the signal line of each net is determined by simulating the operation of each net using simulator 517. Peak current, RMS current and average current is determined.

Abstract: A dielectric capacitor is provided which has a reduced leakage current. The surface of a first electrode (38) of the capacitor is electropolished and a dielectric film (40) and a second electrode (37) are successively laminated on it. The convex parts pointed end (38a) existing on the surface of the first electrode is very finely polished uniformly by dissolving according to electropolishing, a spherical curved surface in which the radius of curvature has been enlarged is formed, and the surface of the first electrode is flattened. Therefore, concentration of electrolysis can be prevented during the operation at the interface of the first electrode and the dielectric film, and the leakage current can be reduced considerably.

Abstract: A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected.

Abstract: A method of removing photoresist material from a semiconductor wafer is disclosed. The method includes rinsing the semiconductor wafer in an organic solvent selected to dissolve the photoresist material. The method next rinses the semiconductor wafer in a light alcohol such as isopropyl alcohol. The method next subjects the semiconductor wafer to an alcohol vapor dry operation. An oxygen plasma ashing operation is then used to oxidize organic material on the semiconductor wafer. This is followed by another rinse. This post ash rinse includes only the light alcohol without the organic solvent. The post ash rinse may include dipping the semiconductor wafers into one or two isopropyl alcohol tanks. Finally is another alcohol vapor dry operation.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus.

Abstract: A data processing apparatus employs write priority to permit a data processing apparatus to execute an if, then, else operation in a single instruction cycle. The data processing apparatus includes pipelined data unit (110) and address unit (120) operations. The address unit (120) data move operation has a higher write priority than the storing of the data unit (110) operation. The data unit (110) includes an arithmetic logic unit (230) that performs an unconditional operation with the result to be stored in a destination register (200). The address unit (120) sets the address for a data move operation to the same destination register (200). The data move operation is conditional upon the if condition set by the instruction and based upon a set of status bits in a status register (210). The status register (210) includes a plurality of status bits set corresponding to a prior arithmetic logic unit (230) result.

Abstract: A semiconductor package (80) is provided that serves to support a semiconductor chip (12). A radial slot (54) is formed in an inner ring (26). Cross-slots (64) and (66) are formed in a corner member (38) of polyimide film (22). The slots (54), (64) and (66) serve to allow independent expansion of various portions of the polyimide film (22) and prevent breakage of contact leads (14), (16), (18) and (20) due to the differences in the thermal coefficient of expansion of the semiconductor material and the polyimide film material.

Abstract: This invention is a technique for summing plural sections of a single data word. The technique uses a repeated process forming larger and larger partial sums. Initially the single data word is rotated one section. The original single data word and the rotated single data word are masked with a mask having "1's" and "0's" in alternate sections. The mask blocks alternate sections so that adjacent sections of the original data word may be summed on a whole data word basis without any overflow disrupting the partial products. The two masked data words are then summed. This sum results in half as many partial sums as before. Each of these larger partial sums now occupies two original sections of the data word. The process can be repeated for these large partial sums. In the preferred embodiment this technique is used with an arithmetic logic unit (230) capable of forming mixed arithmetic and Boolean combinations of three inputs having a barrel rotator (235) driving one input.

Abstract: A computerized method (20, 60) for optimizing chip size/aspect ratio and reticle layout. The method includes the steps of first generating an initial rectangular shot map (22, 62) having a number of rows and columns of shots, determining which chips in the initial rectangular shot map are geometrically positioned on acceptable areas of a wafer, determining which chips in the initial rectangular shot map are geometrically positioned on low and high yield locations of the wafer, and deleting the empty shots from the initial rectangular shot map for obtaining a temporary best shot map. Thereafter, iteratively shifting the initial rectangular shot map along a first axis until a first predetermined limit is reached, comparing each resultant shifted shot map with the temporary best shot map, and setting the shifted shot map as the temporary best shot map in response to a favorable comparison.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Abstract: This invention is a method of decoding a stream of video image data transmitted as independent image frames consisting of plural marcoblocks transmitted in a nonsequential order. The method defines a sub-frame corresponding to a proper subset of the full frame. The method determines if a currently received macroblock is within the sub-frame. The method decodes the sub-frame. The sub-frame may be decoded at less than or equal to the frame rate of the video image data. A table has one entry for each macroblock that stores a transmission order within the video frame for the corresponding macroblock. The method determine if a current macroblock is within the sub-frame by reading the table. Each macroblock consists of a plurality of contiguous blocks and includes luminance data for any included blocks and chrominance data for the macroblock as a whole. The method optionally decodes the luminance data for each included block and ignores the chrominance data.

Abstract: A D flip-flop circuit has two current paths supply the output signal of this flip-flop. A push-pull circuit including an inverter and a transmission gate clocked in a first phase supplies the output of the D flip-flop in a first output path. A slave latch connected to the transmission gate having an output clocked in a second phase opposite to the first phase serves as the second path to the output. In one alternative embodiment the master latch includes a transmission gate clocked in the second phase serving as input and a pair of cross coupled inverters serving as latch. The master latch may include a feedback P-type MOSFET. The slave latch may includes two slave latch inverters and a transmission gate clocked in the second phase connected to the output of the D flip-flop output. In a second alternative, an appropriately clocked tri-state inverter replaces the second slave latch inverter and the transmission gate.

Abstract: A method of producing a computer program for a computer capable of operating in a plurality of disjoint instruction sets. The method produces a plurality of independently callable functions. For each function the method determines a target instruction set employed by the function. The method provides the function with a name corresponding to the target instruction set. The function name is preferably a modification of a user provided function name corresponding to the target instruction set. The method identifies each call of another independent function and provides each with a name corresponding to the target instruction set. The method produces a veneer function for each function and for each other instruction set. The veneer functions include changing the computer from operating in the other instruction set to operating in the target instruction set, calling the corresponding function, changing the computer to operate in the other instruction set, and a return command.

Abstract: A decoded video signal which was encoded in accordance with a standard, such as MPEG-2, is encoded "on the fly" using a lossless linear predicted coding technique and stored in a compressed form in a RAM. A separate encoding technique is provided for B pictures and for I or P pictures. The compressed B pictures are decompressed for display. The compressed I or P pictures are decompressed for display or for use in decoding other P or B pictures.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a Boolean combination of the three inputs that is selected by a function signal. The arithmetic logic unit is capable of forming all possible Boolean combinations of the three inputs. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal optionally comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal optionally comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239).

Abstract: An off-line modeling system (50) is provided for modeling a feedback path and a secondary path by calculating feedback neutralization filter taps and secondary path compensation filter taps. The off-line modeling system (50) includes a reference sensor (16), a secondary source (18), an error sensor (20), and an off-line modeling circuitry (10). The reference sensor (16) receives a noise signal and a feedback signal (22) and generates a primary signal x(n) in response. The secondary source (18) receives a modeling signal v(n) and provides the modeling signal v(n) to the feedback path and the secondary path. The error sensor (20) receives a residual signal generates an error signal e(n). The off-line modeling circuitry (10) receives the primary signal x(n) and the error signal e(n) and generates the modeling signal v(n) while modeling the feedback path and the secondary path.

Abstract: A processor (10) comprises a plurality of processing elements each having an input register (11), first memory bank (12), first sense amplifier (40), ALU (13), output register (16), second memory bank (15) and second sense amplifier (42). The first sense amplifier (40) is shared between the input register (11) and first memory bank (12). The second sense amplifier (42) is shared between the output register (16) and second memory bank (15). The sense amplifier (40,42) may be paused to prevent voltage spikes during a read/write operation, or to wait until a calculation is completed.

Abstract: An apparatus for isolating defects in an integrated circuit using near field scanning photon emission microscopy comprises a photon collector 10 which receives emitted photons 16 from a surface 14 of an energized or biased integrated circuit 12, a CCD camera 20 for converting the photons into an emission image 22, and an optical fiber 18 coupling the CCD camera 20 to the photon collector 10, so that the optical fiber transmits photons from the collector to the CCD camera. As a result, defects in integrated circuits can be isolated with greater resolution than currently available using conventional far field photon emission microscopy.

Abstract: This invention deals with various circuits using transistors having two different threshold voltages designated high threshold voltage (HVT) and low threshold voltage (LVT). These circuits employ the know faster response time of LVT transistors while substantially avoiding the known greater leakage current of LVT transistors. A two input multiplexer includes two transmission gates driven in opposite phases by a selection control signal. One transmission gate, preferably the transmission gate most often selected, includes LVT transistors while the other transmission gate includes HVT transistors. A hybrid threshold voltage D flip-flop circuit employs LVT transistors in input transmission gates of both a master latch and a slave latch. In a conventional circuit, the output invertor of the slave latch also includes LVT transistors. In a split slave dual path circuit, the intermediate inverter also includes LVT transistors.