Abstract: A token passing structure controls alignment fault generation. An alignment fault state circuit stores one of four states corresponding to whether the operating system permits address misalignment fault generation and whether the application program requests such address misalignment fault generation. If the token is present in a particular latch, then the corresponding state is active. If the token is absent, then the corresponding state is inactive. The presence of the token in a predetermined one of the four states causes a fault gate qualifier signal to be active permitting fault generation on address misalignment. Absence of the token from that state causes the fault gate qualifier signal to be inactive prohibiting fault generation on address misalignment. This structure efficiently implements address misalignment fault control by means of token location. Every token location is accessible at every privilege level.

Abstract: A method and apparatus are provided for integrated circuit testing applications. One aspect of the invention is a contactor (10) for test applications. The contactor (10) comprises a membrane carrier (12) having at least one contact (16) on the surface of the carrier (12) electrically connected to at least one terminal (18) on the carrier (12). A pin (14) is metallically bonded to the terminal (18).

Abstract: In accordance with the invention, integrated circuit dies may be packaged in a plastic package employing an area area array technology such as a conductive ball grid array, column grid array or pin grid array. One aspect of the invention is an integrated circuit package (10) which includes an electronic circuit enclosed by a plastic body (12, 14). The molded plastic body has a first major surface opposing a second major surface. The first major surface of integrated circuit (10) has a plurality of openings therein. One of a plurality of conductive pads (18) is adjacent to each one of the openings and is electrically connected to the electronic circuit. Each of a plurality of conductors (20) is electrically connected to one of the pads (18) and protrudes from one of the openings (22).

Abstract: A battery-powered computing system (20) including video decoding capability, particularly as pertinent to the H.263 standard, is disclosed. The system (20) includes a main integrated circuit (30) having an on-chip central processing unit (CPU) (32) and on-chip shared memory (33) for the temporary buffering of video image data that is retrieved and generated during the video decoding process. The CPU (32) is programmed to perform a combined P and B prediction process (46) upon a previously predicted P frame (P.sub.T-1), with accesses to internal buffers in shared memory (33) instead of to main memory (40). Preferably, inverse transform processes (48, 52) also access shared memory (33) rather than main memory (40). The combined P and B prediction process (46) preferably handles unrestricted motion vectors using edge pixels (P.sub.

Abstract: Configurable logic circuit (10,110) and method may comprise a control circuit (12,112) and a logic circuit (14,114). The control circuit (12,112) may generate an intermediate clock function (36,136) in response to selection of one of a first (30,130) and a second (32,132) clock input based on a clock control input (34,134), generate a first control function (46,146) in response to selection of one of a first (40,140) and a second (42,142) control input based on the intermediate clock function (36,136) and generate a second control function (56,156) in response to selection of one of the second (42,142) and a third (52,152) control input based on the intermediate clock function (36,136). The logic circuit (14,114) may be coupled to the control circuit (12,112) and configured into one of a plurality of logic modes in response to a combination of the first (46,146) and second control functions (56,156).

Abstract: An apparatus for detecting cracks in a flip-chip die which comprises an emitter (2) coupled to the die (1) for emitting energy along an axis, a probe (3) located on the die for receiving the energy, and a device (19) coupled to the probe for detecting the energy along the axis.

Abstract: A system (10, 110, 210) for detecting particles (144) on a surface of a substrate-supporting chuck (14, 114, 214) including an inspection subsystem (128, 130, 131, 116, 250, 252, 222, 216) for analyzing the surface of the chuck (14, 114, 214) to determine if any particles (144) are thereon, a movable table (16, 116, 216) for holding the chuck (14, 114, 214) to inspect it and for moving the chuck (14, 114, 214) during inspection, and a control unit (22, 122, 222) for moving the movable table (16, 116, 216) relative to the inspection subsystem (128, 130, 131, 116, 250, 252, 222, 216) to inspect the surface of the chuck (14, 114, 214) and to produce an indication signal if a particle (144) is detected on the surface of the chuck (14, 114, 214).

Abstract: In a microprocessor embodiment (26), the microprocessor is operable to multi-task a plurality of programs, wherein the plurality of programs include a virtual program (38, 40) operable in a virtual mode and a monitor program (36) in a protected mode. The microprocessor includes an interrupt handling circuit (30) for executing an interrupt handler in response to a hardware interrupt request signal (HIM.cndot.INTR). The microprocessor further includes an interrupt flag bit (IF) set in a like manner in both the virtual mode and the protected mode. The interrupt flag bit is set in a first state to inhibit receipt of the hardware interrupt request signal by the interrupt handling circuit, and the interrupt flag bit is set in a second state to enable receipt of the hardware interrupt request signal by the interrupt handling circuit. The microprocessor further includes a virtual mode control signal (VM.cndot.

Abstract: An improved microcomputer has a page register connected to a program counter in order to extend the program address range of the microcomputer. A page stack is connected to the pager register and operates in conjunction with an address stack. The page register is loaded from bits in the first word of a two word branch or call instruction in such a manner that no additional execution time is required nor are any additional instructions required to provide the extended address range. A predefined microprocessor ASIC cell is augmented by externally connecting a page register and an opcode decoder so that instruction memory address range can be expanded by paging without redesigning the microprocessor cell.

Abstract: A method and apparatus for receiving an input digital data signal representing a sequence of values in which samples of the waveform of the data signal are taken a plurality of times during each of the values. A plurality of the samples are stored as they are received, in a known order in locations at a sequence of addresses in a memory. A digital signal representing the difference in phase between the input data signal and a reference signal is derived. The digital phase signal is decoded and the location at the address of the memory represented by the digital phase signal is accessed so as to select samples remote from edges in the waveform of the input data signal.

Abstract: A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal.

Abstract: A method of making ferroelectric film capacitors with sufficient yield for application to ULSI. In a first embodiment, after formation of a first ferroelectric film as the capacitor ferroelectric film, a very thin second ferroelectric film is deposited to fill the cavity portions generated between the crystal grains. This reduces the leakage current and increases the capacitor yield. In second embodiment, the cavity portions are filled with an insulating layer.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Abstract: Integrated circuit architectures and methods of operation are provided that allow for the connection of a negative back-gate bias voltage to substrate contacts 24, 90, and 56 during burn-in operations. Accordingly, latch up conditions are prevented during burn-in operations when a circuit is especially vulnerable to such conditions and a grounded substrate is provided to allow for the most efficient operation of the circuit during normal conditions.

Abstract: A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).

Abstract: A processor processes a plurality of instructions according to a disclosed method. First, the method receives (32) an instruction from the plurality of instructions. Second, the method determines (34) whether the received instruction is preceded by an instruction path leading code. Third, the method passes (36 or 38) the received instruction along at least one instruction path in a plurality of instruction paths. Fourth, in response to determining that the received instruction is preceded by an instruction path leading code, the method executes a machine word corresponding to the received instruction and selected from one of the plurality of instruction paths. Specifically, the selected instruction path is selected in response to the instruction path leading code.

Abstract: A system (12) for delivering spin-on-glass (SOG) to a substrate (14) has a spin chuck (16) for spinning a substrate (14), a delivery nozzle (18, 118, 218, 318, 418) having an interior conduit (419), a delivery nozzle-positioning subsystem (62) coupled to the delivery nozzle (18, 118, 218, 318, 418) for selectively positioning the delivery nozzle (18, 118, 218, 318, 418) over the spin chuck (16) for delivery of SOG, a SOG supply line (60, 160, 360) for supplying SOG, a cleaning fluid supply line (22, 122, 322) for supplying a cleaning fluid used to remove dried SOG, and a valve subsystem (20, 120, 320) fluidly coupled to the SOG supply line (60, 160, 360), cleaning-fluid supply line (22, 122, 322), and delivery nozzle (18, 118, 218, 318, 418) for selectively delivering SOG or a cleaning fluid through the interior conduit (419) of the delivery nozzle (18, 118, 218, 318, 418). A cleaning station 466 may be used to clean an exterior (421) of the nozzle (18, 118 218, 318, 418).

Abstract: A method for forming a sum of the absolute value of the difference between each pair of numbers of respective first and second sets of numbers. The method includes forming the difference between corresponding numbers of the first and second sets. This difference is either added to or subtracted from a running sum based upon its sign. This is repeated for all number pairs. Preferably, the initial subtraction sets a status bit in a flag register (211) which controls the selection of addition or subtraction. The conditional addition to or subtraction from the running sum may generate a carry-out representing the most significant bit of the running sum. This carry-out is preferably stored and later added to the running sum to recover the most significant overflow bits. This technique is preferably practiced using an arithmetic logic unit (230) that can be split into plural independent sections (301, 302, 303, 304).

Abstract: A microprocessor has an internal cache memory which can cache a mix of normal system memory and system management mode memory. An address translator passes an address unchanged if a system management mode input signal indicates the normal mode. The address translator translates the address to an address range outside a range of addresses occupied by the external memory when in the system management mode. A cache memory is connected to the address translator for caching data with address tags corresponding to an address received from the address translator. The address translator preferably includes an address range comparator comparing the address with a predetermined address range. The address translation may be combined with virtual memory to physical memory address translation. An inverse address translator handles cache line writeback.

Abstract: A multilevel hierarchical least recently used cache replacement priority in a digital data processing system including plural memories, each memory connected to said system bus for memory access, a memory address generator generating addresses for read access to a corresponding of the memories and a memory cache having a plurality of cache entries, each cache entry including a range of addresses and a predetermined set of cache words. During each memory read the comparator compares the generated address with the address range of each cache entry. If there is a match, then the cache supplies a cache word corresponding to the least significant bits of the generated address from the matching cache entry. If there is no such match, the generated address is supplied to the memories and a set of words is recalled corresponding to the generated address. This set of words replaces a least recently used prior stored memory cache entry having the lowest priority level.