Abstract: A multiplexer has first, second, third and fourth inputs receiving respective first, second, third and fourth input signals, having first and second control inputs receiving respective first and second select input signals and an output. Each of the four input signals is supplied to the input of a CMOS transmission gate. The first and second transmission gates are clocked via the first select signal and its inverse in a first phase. The third and fourth transmission gates are clocked via the first select signal and its inverse in a second phase, opposite to the first phase. A first embodiment includes a first intermediate inverter having an input connected jointly to the outputs of the first and second transmission gates and a second intermediate inverter having an input connected jointly to the outputs of the third and fourth transmission gates.

Abstract: A programmable logic device, such as a digital signal processor (DSP) (130), having a Euclidean array unit (115; 115') is disclosed. The Euclidean array unit (115; 115') is arranged to perform finite field arithmetic functions useful in determining the greatest common factor among two polynomial series, in a sequential fashion beginning with a highest order pair of operands (A.sub.0, B.sub.0) and proceeding along the sequence. A source register (SRC) receives each pair of operands, and the results are stored in a result register (RES) in reverse order, prior to writing the results in memory. As a result, B result values are stored in the same location as the A input operand, and vice versa. This reversal of memory locations permits successive passes of the Euclidean operation to be carried out with simple incrementing of the starting byte address (SBA) at which the operands are located in memory, thus eliminating the need for large memory shifts.

Abstract: In a preferred method embodiment, the method operates a microprocessor (36). The method fetches (14) a short backward branch loop (34) of instructions, wherein the short backward branch loop comprises a branch instruction (SSB) and a target instruction (TR) The method also determines that the short backward branch instruction is a short backward branch instruction after fetching it. Still further, the method stores (30) a short backward branch loop of execution unit instructions. This short backward branch loop comprises a branch execution unit instruction (SSB) and a target execution unit instruction (TR). Additionally, without re-fetching the short backward branch loop after the storing step, the method also executes (22) a plurality of iterations of the short backward branch loop of execution unit instructions over a plurality of clock cycles.

Abstract: A method is provided for forming non-overlapping clock signals 402 and 404 for an integrated circuit. A reference clock 300 whose frequency is twice that of a desired operating frequency for the integrated circuit is used. A master clock signal is formed which has a high pulse width T9a which is approximately the same as the high pulse width of the reference clock, but the frequency of the master clock is one half the frequency of the reference clock. Likewise, a slave clock signal is formed which has a high pulse width T10a which is approximately the same as the high pulse width of the reference clock, but the frequency of the slave clock is also one half the frequency of the reference clock. The high pulse width of either or both the master clock signal and slave clock signal is then widened by an analog delay means, but by an amount T13 and T14 which is less than the low pulse width of the reference clock, so that the master clock signal and the slave clock signal do not overlap each other.

Abstract: A high power MOS transistor consists of a large number of sub-transistors (T1 to T6) connected in parallel. The gate electrodes of the sub-transistors (T1 to T6) can be driven individually via controllable switching elements (SW1 to SW6; SQ1 to SQ5).

Abstract: In a method embodiment (34), the method operates a computer system (10) having a type of configuration and including a single integrated circuit microprocessor (24). The microprocessor operates in response to codes and has an instruction set. The method involves various steps, including determining (40) the type of the configuration. In response to the type of the configuration, the method selects (42) a set of patch codes from a plurality of sets of patch codes. The method also issues (54) a patch request instruction from the instruction set, and it stores (56) the selected set of patch codes to a memory space accessible by the microprocessor.

Abstract: A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present.

Abstract: A data processing device is programmed to decode and transform a stream of data representing a plurality of subband encoded channels of audio data into one or more channels of PCM encoded data for reproduction by a speaker subsystem. An improved method for decoding and transforming utilizes downmix matrices (1021 and 1022) to form downmixed frequency domain channels in buffers (1031-1034). Only two long DCT transform operations (1041 and 1042) and two short DCT transform operations (1043 and 1044) are needed to transform the downmixed frequency domain channels into a left PCM output (1071) and a right PCM output (1072).

Abstract: A feedforward active noise control system (50) is provided that includes a reference sensor (16), a secondary source (18), an error sensor (20), and an active noise control system controller (10) for generating an anti-noise signal to attenuate a noise signal provided through a media. The feedforward active noise control system (50) performs on-line feedback path modeling and on-line secondary path modeling.

Abstract: A microprocessor (5) having an on-chip floating-point unit, or FPU, (31) is disclosed. Snoop logic (37) is present in the integer pipeline to detect the presence of floating-point load instructions, in which floating-point operands are retrieved from system main memory or from on-chip cache memory (6, 16.sub.d, 18) by load/store units 40. For such operations in which the floating-point operands are of single precision or double precision, immediate formatter (70) receives the retrieved operands on load/store buses (LOAD.sub.-- DATA0, LOAD.sub.-- DATA1) and reformats the operands into a higher precision format for use internally by FPU (31). Rebias circuitry (78) is provided within immediate formatter (70) to change the bias of the exponent portion of the reformatted floating-point operands.

Abstract: An interactive environment is provided for integrated circuit (IC) designers to do an emulation session on a hardware accelerator 111 and then move to simulator 131, and vice versa. An aspect of the present inventive solution swaps memory state and logic storage node state (such as flip-flops and latches) between the accelerator 111 and simulator 131. A complete context switch is performed to create a time shared environment on hardware accelerator 111 so that multiple IC designers can access and use the accelerator. Multiple memory pages can be incorporated to minimize state swap time. Multiple accelerators 111 can be interconnected with a plurality of simulators 131 and a plurality of workstations 101 to allow multiple designers to do interactive operations and allows shifting back and forth between hardware emulation and software simulation.

Abstract: A data processing device 100 uses a portion of a random access memory 111 as an input buffer for holding a portion of a stream of data which is received by an input interface 130. Likewise, a portion of a memory 121 is used as an output buffer for holding a portion of processed data which is output by an output interface 140. A processing unit 110 within the processing device manages the flow of input and output data. The input interface asserts an I/O request 860 when it receives a data word, and the output interface asserts an I/O request 870 when it needs a data word. In response to an I/O request, fast interrupt circuitry inserts a ghost instruction which is formed by doppelganger circuitry into an instruction sequence which is being accessed from a ROM 112. The ghost instruction performs the requested data transfer.

Abstract: For most `natural` signals like audio and video, the first derivative with respect to time (or spatially as in video) can have a significant amount of error and still be perceived as accurate due to the masking properties of the ears and eyes. A Logarithmic Differential Compression (LDC) data stream representation of the first derivative is formed with four or less bits of mantissa and can be treated as both a logarithmic numeric representation and a floating point numeric representation without correction. A digital signal processor 524 is described which performs multiplication of LDC data with a simple scalar adder 600 and addition of LDC data with a simple four or less bit floating point adder 610. A digital signal processor is optimized to process LDC data and low cost arrays of these digital signal processors are formed to provide high performance systems for transforms and filtering.

Abstract: There is disclosed a multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, on a cycle by cycle basis, be grouped in any configuration to run in synchronism (but from different instruction streams) with the other processors in that group. More than one such synchronized group can be formed concurrently. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip.

Abstract: A multiply accumulate unit processes a signal according to a sum-of-products function based upon a plurality of multibit sampled values and a corresponding plurality of multibit constants. A multiply-add block receives the sampled values and the constants. A portion of each constant is selected. A plurality of multipliers multiple sampled values and selected portions of the corresponding constants. The products are added and shifted corresponding to the significance of the selected portion of the constants. These are added to generate a sum of sequential outputs of the multiply-add block. The multiply accumulate unit repeats operation employing the same sample values but portions of said corresponding constants having sequentially less significant bits. This sequence repeats until the sum of all prior sum-of-products functions has a desired level of accuracy.

Abstract: In a pipeline data processor (11), an address pipeline (39, 41) id provided to hold the addresses of the instructions presently in the instruction pipeline (23, 25). The address pipeline facilitates tracing only executed instructions, and permits stopping the data processor during a branch delay slot without losing the branch information.

Abstract: A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 in substrate 150. A thin epitaxial layer 156 is formed on the substrate which overlies the initial high voltage tank and Diffusion Under Film, DUF, region 154. The high voltage tank is extended through the epitaxial layer and power transistor 146 is formed in the high voltage tank and high frequency bipolar transistor 147 is formed in the epitaxial layer using the DUF region as a deep collector. Other types of low voltage devices 139 and 140 and mid voltage devices 141-145 and 148-149 are formed unaffected by the presence of epitaxial layer 156. A single chip transmitter 400 and a single chip receiver 410 is fabricated with high frequency transistors and power devices.

Abstract: A microprocessor (10) and system (2) including a multi-stream pipeline unit (25) are disclosed. The multi-stream pipeline unit (25) includes individual fetch units (26), instruction caches (16.sub.i), and decoders (34) in separate instruction streams (PROC0, PROC1) or pipelines. A common scheduler (36) is provided to check for dependencies among the instructions from the multiple instruction streams (PROC0, PROC1), and to launch instructions for execution by the various execution units (31, 40, 42, 50), including a microcode unit (47). A common register file (39) includes register banks (70) dedicated to each pipeline, and also a register bank (72) that includes temporary and shared registers available to instructions of either instruction stream (PROC0, PROC1), such as useful in the event of register renaming due to a dependency. Each decoded instruction in the scheduler (36) has an identifier (PROC) indicating the one of the instruction streams (PROC0, PROC1) from which it was issued.

Abstract: A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 in substrate 150. A thin epitaxial layer 156 is formed on the substrate which overlies the initial high voltage tank and Diffusion Under Film, DUF, region 154. The high voltage tank is extended through the epitaxial layer and power transistor 146 is formed in the high voltage tank and high frequency bipolar transistor 147 is formed in the epitaxial layer using the DUF region as a deep collector. Other types of low voltage devices 139 and 140 and mid voltage devices 141-145 and 148-149 are formed unaffected by the presence of epitaxial layer 156. A single chip transmitter 400 and a single chip receiver 410 is fabricated with high frequency transistors and power devices.

Abstract: Circuits, systems, and methods of operating a processor (110) to process a plurality of instructions, wherein each of the plurality of instructions has a respective sequence number. Further, selected ones of the plurality of instructions are for accessing a non-register memory (18). For each of the selected ones of the plurality of instructions, the method comprises the following steps. One step (24) receives the instruction and another (26) decodes the received instruction. Yet another step (30) stores a plurality of instruction characteristics in a table (14), wherein the characteristics include the sequence number of the instruction, an identifier of the non-register memory to be accessed by the instruction, and a correlation identifier of the non-register memory to a physical register.