Abstract: A method of operating a microprocessor (12) having an on-chip storage resource (100a). The method first receives a data fetching instruction into an instruction pipeline (38) at a first time. The instruction pipeline has a preliminary stage (40), a plurality of stages (42 through 46) following the preliminary stage, and an execution stage (48) following the plurality of stages. The step of receiving a data fetching instruction at the first time comprises receiving the data fetching instruction in the preliminary stage. The method second performs various steps, including fetching a first data quantity (MRU TARGET DATA) for the data fetching instruction to complete the execution stage of the pipeline, completing the execution stage in connection with the data fetching instruction using the first data quantity, and storing the first data quantity in the on-chip storage resource. The method third receives the data fetching instruction into the preliminary stage at a second time (108).

Abstract: An integrated circuit (2210) provides on a single chip for use with a first processor (106) off-chip, the following combination: first terminals (of 2232) for first processor-related signals and defining a first data width (32-bit), second terminals for external bus-related signals (PCI), third terminals for memory-related signals (of 2258), and a DRAM memory controller (2250) connected to the third terminals. Further on chip is provided an arbiter circuit (2230), a bus bridge circuit (2236) coupled to the DRAM memory controller and to the second terminals, the bus bridge (2236) also coupled to the arbiter (2230), a second processor (2224) having a second data width (16-bit), and a bus interface circuit (2220) coupling the second data width of the second processor (2224) to the first data width. The bus interface circuit (2220) further has bus master and bus slave circuitry coupled between the second processor (2224) and the arbiter circuit (2230).

Abstract: A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present.

Abstract: A clock acquisition subsystem for a data processing system has an interlocked clock multiplexer 100 for acquiring a clock source which is provided as clock signal 102 to the data processing system. Multiplexer 100 has at least two inputs 104 and 106 for clock source signals. Each clock source signal can be connected to one or more clock sources 710 and 720. Control register 730 specifies which clock source is to be selected by the multiplexer. The multiplexer has an interlocked synchronizer on each clock signal input so that when the multiplexer is switched, output clock signal 102 transitions cleanly from a first clock source to a second clock source without glitches or runt pulses. While the data processing system is in a deep sleep low power mode, wakeup logic 750 can provide wakeup signal 751 to power down select logic 740 which automatically selects secondary clock 720 until primary clock 710 is operational.

Abstract: An integrated circuit is provided having a core circuit for performing a plurality of functions, a first pad for receiving an emulator output signal, a pulldown device connected to said first pad, a first logic circuit having an input connected to said first pad and an output signal for enabling emulator signals, a first plurality of second pads for receiving emulator signals, and a first plurality of second logic circuits with each circuit having a first input individually connected to one of said second pads, having a second input connected to said output signal from said first logic circuit, and having an output connected to a portion of said core circuit.

Abstract: A method for testing a digital processor 11 in which a test port 1149 is used to transfer trace data from the digital processor to a test host processor 1101 under control of a user definable program which executes in response to predetermined events on the digital processor. Trace data is gathered while an application program loaded in program memory 61 is executed by the digital processor. Trace data is temporarily stored in a trace region 99 of data memory 25 by user definable code which is executed in a background manner by the digital processor in response to trigger events. The trigger events are also enabled by user definable code which enables various portions of analysis hardware 1217. Trace data is transferred from the digital processor to the test host processor through test port 1149 by sending a notification signal to the test host processor by means of message passing register 1216.

Abstract: A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, on a cycle by cycle basis, be grouped in any configuration to run in synchronism (but from different instruction streams) with the other processors in that group. More than one such synchronized group can be formed concurrently. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip.

Abstract: A microprocessor comprising an instruction pipeline (36) comprising a plurality of successive instruction stages. An instruction passes from a beginning stage (38), through a plurality of intermediary stages (40 through 52), and to an ending stage (54) of the plurality of successive instruction stages. The microprocessor also comprises a storage circuit (58) coupled to receive program thread information output from a first stage (48) of the intermediary stages. Still further, the microprocessor comprises selection circuitry (56) comprising a first input, a second input, and an output for outputting output information from its first and second inputs. The first input of the selection circuitry is coupled to receive output information output from the first stage. The second input of the selection circuitry is coupled to receive program thread information output from the storage circuit.

Abstract: Method and device for enabling high-speed write/read operation of image information in units of blocks, so as to fully meet the demand on high-speed operation of MPEG, etc. Eight memory arrays MA1-MA8 are parallelly-connected in image memory unit 10; hence, in each memory array MAi, image can be written/read individually under control of write address generating circuit 12, memory array control logic 14, and read address generating circuit 16. The input/output terminals of memory arrays MA1-MA8 are connected to half-pel operation circuit 24 through eight data registers DREG1-DREG8 of input/output buffer 18, eight row selectors YSEL1-YSEL8 and column selector XSEL of selector circuit 20, and data bus 22.

Abstract: This device includes, connected in parallel with each of the elements (I, II), corresponding shunt regulators (S11, R11, S21, R21) linked together in series, and the control electrodes of which are connected to networks of resistors which represent voltages of the elements which can be applied to respective comparators (C11, C12, C21, C22) of the lower and upper threshold voltages (Vth11, Vth12, Vth21, Vth22) of the elements with a reference voltage delivered by a reference voltage source (Vref), a switching MOSFET transistor (4), with low conduction resistance and with defined off-state impedance, connected between the most negative terminal of the set of elements (II) in series and the negative terminal (Vbat-) of the protection device and means of control of the MOSFET transistor from output signals from the comparators (C11, C12, C21, C22) in order to alter the state of the said MOSFET transistor (4) for the purpose of regulating the state of charge and of discharge of the elements (I, II).

Abstract: This devise comprising a digital signal processor (1) proper, a ROM program memory (2) and a RAM data memory (3) which are connected respectively to the processor, is characterized in that associated with the RAM data memory is a RAM viterbi memory (7) including means for executing addition, comparison and selection operations of the Viterbi algorithm, and logic (8) for controlling the Viterbi memory (7).

Abstract: A data processing device uses a portion of random access memory 121 as an output buffer 124 for holding a portion of a stream of PCM data which is to be output to a digital to analog converter 530. D/A 530 forms a left analog channel and a right analog channel for speaker subsystems 814 and 815. The PCM data stream is stored in the output buffer so that PCM data samples which pertain to the left channel are stored at even address and PCM data samples which pertain to the right channel are stored at odd address. Control circuitry 145 monitors direct memory access (DMA) transfers which transfer PCM data samples to PCM serializer 142. By comparing the address of each DMA transfer to a left/right channel signal from the D/A, the control circuitry can verify that channel synchronization is correct. If a synchronization error is detected, an channel synchronization error correction procedure is invoked.

Abstract: A method of reading a memory cell containing an access transistor, a word line and a memory storage for holding information. The access transistor having a control terminal is connected to the word line. The memory storage is connected to the access transistor and thereby to a sense amplifier through a bit line. The access transistor, operating in a conductive state, is responsive to the word line. The bit line is precharged to an intermediate voltage level greater than a low threshold level and less than an upper limit level. The bit line is discharged from the intermediate voltage level to produce a low voltage level in a prescribed time if the memory storage holds memory information of a first state. The bit line is charged to approximately the upper limit level in the prescribed time if the memory storage holds memory information of a second state. The voltage of the bit line is determined by the sense amplifier after the prescribed time so that the memory information is read.

Abstract: A method of making ferroelectric film capacitors with sufficient yield for application to ULSI. In a first embodiment, after formation of a first ferroelectric film as the capacitor ferroelectric film, a very thin second ferroelectric film is deposited to fill the cavity portions generated between the crystal grains. This reduces the leakage current and increases the capacitor yield. In second embodiment, the cavity portions are filled with an insulating layer.

Abstract: An audio data processing system having a control processor coupled to an execution controller through a bus is provided. The control processor serves as a master processor to control the operation of the execution controller which in turn controls the execution of a multiplier accumulator. An ancillary data handler is provided to retrieve ancillary data from an input first in/first out (FIFO) buffer. Audio data is retrieved from the input buffer by the control processor and processed data is output through an output block.

Abstract: This invention relates to a high-resolution digital/analogue converter intended in particular for the tuning of a voltage-controlled quartz oscillator. This converter comprises a first second-order Sigma-Delta modulator (1) to the output of which is connected the input of a second Sigma-Delta modulator (9) producing a single bit at its output and a digital/analogue conversion circuit (13). The circuit of the converter furthermore comprises means for filtering the high-frequency components of the signal undergoing processing so as to obtain a quasi-stable D.C. voltage source with a high resolution.This invention is applicable to any voltage-controlled system having large inertia, and in particular, voltage-controlled quartz oscillators and transducers.

Abstract: This is a method and apparatus for waking up an integrated circuit 10 which has been placed into a low power mode in response to an idle instruction or the like. A plurality of wakeup reset signals 320 and wakeup interrupt signals 330 are provided to wakeup circuitry 300 in order to initiate a wake-up process. Wakeup circuitry 300 conditions signals 320 and signals 330 so that a wake-up process is initiated only when the integrated circuit is in a low power mode; therefore, signals 320 and signals 330 can be used for other purposes when the integrated circuit is not in a low power mode. By such conditioning, no additional pins are required on integrated circuit 10 to provide a plurality of wake-up stimuli.

Abstract: A data processing device uses a portion of a random access memory as an input buffer 114 for holding a portion of a stream of data which is being processed by a processing unit within the processing device. A Get Bit-Field instruction is provided which directs the processing unit to extract selected bit fields from the data stream stored in the input buffer. A register R6 holds a bit address which points to the end of a selected bit field, while a register R0 holds the width of the selected bit field. An address register is connected to a register R6 in a manner that allows data words to be accessed in input buffer 114 using only a word portion of the bit address. A funnel shifter 203 is disposed to extract the selected bit field from concatenated data words in response to a bit address portion of the bit address in register R6.

Abstract: A method of testing an integrated circuit 104 which may have multiple modules 204a-d is provided. Target interface 200 provides an interface for connecting target system 104 to a test system which is an extension of IEEE 1149.1. Target system 104 may have multiple devices 202, each having multiple modules 204. Each device 202 has device interface 210 which connects to target interface 200. Decoder 1020 decodes certain signals from interface 200 to enable Extended Operating Modes which allow test codes to be easily directed to any one of modules 204a-d. Hardware and software debugging of system 104 is aided by interface 200 and production testing of system 104 is simplified.

Abstract: This is a method for improving contact openings during the manufacture of an integrated circuit. The process of forming a contact in an integrated circuit is often carried out rapidly, with imperfect control. As a result, incomplete removal of the insulating material may occur within the contact opening. In addition, the substrate material may be damaged to some extent within the contact opening by the contact formation process. In either case, high electrical resistance within the contact may result. Photo-resist may leave residue within the contact opening, low surface dopant concentrations, and insulative layer discontinuities may cause increased electrical resistance within the contact. A sequential application of two types of aqueous etchants will smooth the contact sidewall and remove a thin layer of relatively low dopant concentration at the surface of the substrate and other debris which may remain from the contact formation process and thereby allow lower resistance contacts to be formed.