Patents Represented by Attorney, Agent or Law Firm Gerald Maliszewski
  • Patent number: 7571429
    Abstract: A system and method are provided for reporting errors in an object-oriented software architecture environment. The method comprises: an application calling an initial method; in response to the initial method call, at least one object encountering an error in response to a subsequent method call; accumulating error information; and, creating a user-defined accumulated error report. Generally, accumulating error information includes: calling an accumulated error reporting object; and, from the accumulated error report object, calling a method for adding received error information to accumulated error information. Then, creating the user-defined accumulated error report includes calling a method for creating an error report text message by: reviewing the accumulated error information; and, matching accumulated error information with user-selected error criteria.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: August 4, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sridhar Dathathraya, David John Lovat
  • Patent number: 7570834
    Abstract: An image de-ringing filter system and method are provided. The method comprises: accepting image pixels; collecting data from a first group of pixels neighboring a test pixel; in response to the first group data, deciding if the test pixel includes image ringing artifacts; collecting data from a second group of pixels neighboring the test pixel; in response to the second group data, generating a filtered value (FV); and, replacing the test pixel actual value with FV. Typically, collecting data from the first and second group of pixels includes the performance of a mathematical operation. For example, a matrix may be defined for the multiplication of the first group of pixels. Values of pixels on a first side of the coordinate axis may be subtracted from pixels on a second side of the coordinate axis, opposite of the first side. Then, the difference is compared to a threshold.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: August 4, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Sachin Govind Deshpande
  • Patent number: 7564267
    Abstract: A thermal electric binary logic circuit is provided along with a method for switching a thermal electric binary logic circuit. The method accepts an input voltage representing an input logic state and generates a thermal electric (TE) temperature value in response to the input voltage. Then, in response to the TE temperature value, a TE voltage is generated and supplied as an output voltage representing an output logic state. In one aspect, a first TE element is connected to the input voltage and to a current source/sink having an intermediate voltage. As a result, the first TE element generates a first temperature reference. A second TE thermally is connected to the first TE, electrically connected to a first voltage reference, and electrically connected to an output to supply the output voltage. As a result, a first voltage varies across the second TE in response to the first temperature.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: July 21, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Joseph Martin Patterson
  • Patent number: 7561801
    Abstract: A ring connection system and method are providing for distributing signals in an optical-to-electrical interface. The method electrically connects a plurality of nodes in a series-connecting ring, and receives an optical signal at a first node from a service provider. The method converts the optical signal to an electrical signal, and distributes the electrical signal via the ring. At each node, the electrical signal is supplied from a customer interface. Typically, each node has a plurality of customer interfaces. In one aspect, ITU-T G.984.3 Giagbit-capable Passive Optical Network (GPON) optical signals are received converted to a customer interface electrical signal such as an Ethernet connecting transfer mode, or time division multiplexed signal. Electrically connecting the plurality of nodes in the series-connected ring includes: series connecting the nodes in a North ring; and, series connecting the nodes in a South ring, opposite in direction from the North ring.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: July 14, 2009
    Assignee: Applied Micro Circuits Corporation
    Inventors: Glen Miller, Armin Schulz, Timothy P. Walker
  • Patent number: 7557937
    Abstract: A system and method are provided for interpreting time stamp information from a digital camera. The method comprises: opening a first format interpreter; receiving image information from a digital camera in a first format selected from the group including joint photographic experts group (JPEG) and tagged image file format (TIFF) formats, with a corresponding time stamp information; displaying the images with corresponding time stamps for editing; selecting the “print time stamp” option; selecting a time stamp layout for a corresponding image; converting the image information and time stamp information to bitmap information; and, supplying the edited images with corresponding time stamps for printing. Some aspects of the method further comprise: selecting miscellaneous superposition overlays for corresponding images.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: July 7, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Jiaping Song
  • Patent number: 7544625
    Abstract: A method is provided for forming a silicon oxide (SiOx) thin-film with embedded nanocrystalline silicon (Si). The method deposits SiOx, where x is in the range of 1 to 2, overlying a substrate, using a high-density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, the SiOx thin-film is embedded with nanocrystalline Si. The HD PECVD process may use an inductively coupled plasma (ICP) source, a substrate temperature of less than about 400° C., and an oxygen source gas with a silicon precursor. In one aspect, a hydrogen source gas and an inert gas are used, where the ratio of oxygen source gas to inert gas is in the range of about 0.02 to 5. The SiOx thin-film with embedded nanocrystalline Si typically has a refractive index in the range of about 1.6 to 2.2, with an extinction coefficient in the range of 0 to 0.5.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: June 9, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Pooran Chandra Joshi, Tingkai Li, Yoshi Ono, Apostolos T. Voutsas, John W. Hartzell
  • Patent number: 7543034
    Abstract: A system and method are provided for establishing an Instant Messenger (IM) reflector service. The method comprises: establishing an interface between an IM network server and an IM master client identified with a first username; establishing a reflector service between the IM master client and an IM peer client; and, identifying the IM peer client with the first username. That is, IM messages associated with the first username are routed via the IM master client. Alternately stated, IM messages are communicated between the IM network and all IM clients identified with the first username. More specifically, communicating IM messages with all IM clients identified with the first username includes: the IM master client receiving IM messages from the IM network, addressed to the first username; and, the IM master client distributing the IM messages to IM peer clients identified with the first username, via the reflector service.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: June 2, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Sachin Govind Deshpande
  • Patent number: 7532187
    Abstract: A dual-gate thin-film transistor (DG-TFT) voltage storage circuit is provided. The circuit includes a voltage storage element, a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a first gate line, a second S/D region connected to the voltage storage element, and a bottom gate connected to a bias line. In one aspect, the circuit further includes a voltage shifter having an input connected to the first gate line and an output to supply a bias voltage on the bias line. Examples of a voltage storage element include a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: May 12, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Themistokles Afentakis, Apostolos T. Voutsas, Paul J. Schuele
  • Patent number: 7528695
    Abstract: A method of selectively enhancing the sensitivity of a metal oxide sensor includes fabricating a ZnO sensor having a ZnO sensor element therein; and exposing the ZnO sensor element to a plasma stream.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: May 5, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: John F. Conley, Jr., Yoshi Ono
  • Patent number: 7529329
    Abstract: A clock and data recovery circuit (CDR) for receiving high-speed digital data, and having an analog phase offset control capability, is improved by providing an adaptive sampling edge position control. A differential circuit samples the raw data signal at three closely spaced sampling points of the eye, and compares advanced and delayed sampled data with the nominal sampled data. If either the advanced or delayed sampled data differ from the nominal sampled data, i.e. if advanced or delayed errors are detected, a shift in the sampling edge position may be required. A logic circuit performs a method determining the occurrence of advanced or delayed errors over progressively longer time intervals, and to adjust the sampling edge position of the CDR by controlling the phase offset.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: May 5, 2009
    Assignee: Applied Micro Circuits Corporation
    Inventors: Petre Popescu, Douglas Stuart McPherson, Hai Tran Quoc, Stanislas Wolski
  • Patent number: 7525382
    Abstract: A buffer amplifier and an associated method have been provided for slew rate and swing level control in the buffering of a signal. The method accepts an input signal having a voltage swing, a swing control signal, and a slew rate control signal. The voltage swing for each output in a set of serially-connected buffer stages is selected in response to the swing control signal. The selected voltage swing for a subset of buffer stages is modified in response to the slew rate control signal. Selecting the voltage swing for each output entails selecting a source current for each buffer stage. A bias current is generated and mirrored through a current source connected to each buffer stage. Modifying the selected voltage swing for each of the subset of buffer stages includes modifying the bias current to the subset of buffer stages.
    Type: Grant
    Filed: August 4, 2007
    Date of Patent: April 28, 2009
    Assignee: Applied Micro Circuits Corporation
    Inventors: Hongming An, Sudhaker Anumula, Howard Chang
  • Patent number: 7515315
    Abstract: A scan description language (SDL) system and method are provided for managing a scan job. The method comprises: scanning a document at a scanning device; constructing a scan job using SDL commands; partially performing the scan job at the scanning device in response to the SDL commands; and, partially performing the scan job at a node connected to the scanning device in response to the SDL commands. The scan job can be constructed at a scanning device front panel, a connected web page, or a client connected to the scanning device. Likewise, the scan job can be initiated from a front panel of the scanning device, a connected client, or a connected web page. Further, the scan job may be partially performed a locally connected client, a network-connected client, a network-connected server, a locally connected server, another scanning device, or a telephone network-connected client.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: April 7, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Andrew Rodney Ferlitsch
  • Patent number: 7514282
    Abstract: An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: April 7, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Tingkai Li, Jong-Jan Lee, Jer-Shen Maa, Sheng Teng Hsu
  • Patent number: 7509341
    Abstract: A stateless-object method is provided for executing instructions. The method: establishes a central repository of states, cross-referencing state locations in memory, to identifiers; calls a first method; accesses a stateless-object in response to the first method, the stateless-object including an identifier and a second method; reads the identifier; uses the identifier to cross-reference the stateless-object's state location in the repository; accesses the located state; and, instantiates the second method in response to accessing the state. The central repository of states may cross-reference a first state to a first identifier, and the step of accessing the stateless-object includes accessing a plurality of stateless-objects in response to the first method, with each of the stateless-objects including the first identifier.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: March 24, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Michael Constantin, David J. Lovat
  • Patent number: 7494840
    Abstract: An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x?4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: February 24, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Fengyan Zhang, Sheng Teng Hsu
  • Patent number: 7473640
    Abstract: A method, and corresponding transistor structure are provided for protecting the gate electrode from an underlying gate insulator. The method comprises: forming a gate insulator overlying a channel region; forming a first metal barrier overlying the gate insulator, having a thickness of less than 5 nanometers (nm); forming a second metal gate electrode overlying the first metal barrier, having a thickness of greater than 10 nm; and, establishing a gate electrode work function exclusively responsive to the second metal. The second metal gate electrode can be one of the following materials: elementary metals such as p+ poly, n+ poly. Ta, W, Re, RuO2, Pt, Ti, Hf, Zr, Cu, V, Ir, Ni, Mn, Co, NbO, Pd, Mo, TaSiN, and Nb, and binary metals such as WN, TaN, and TiN. The first metal barrier can be a binary metal, such as TaN, TiN, or WN.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: January 6, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: John F. Conley, Jr., Yoshi Ono, Wei Gao
  • Patent number: 7473150
    Abstract: A method is provided for forming a ZnO Si N—I—N EL device. The method comprises: forming an n-doped Si layer; forming a Si oxide (SiO2) layer overlying the n-doped Si layer; forming an n-type ZnO layer overlying the SiO2 layer; and, forming an electrode overlying the ZnO layer. The electrode can be a transparent material such as indium tin oxide, zinc oxyfluoride, or a conductive plastic. The n-doped Si layer can be polycrystalline or single-crystal Si. In some aspects, the Si oxide layer has a thickness in the range of 1 to 20 nm. More preferably, the thickness is 2 to 5 nm. The ZnO layer thickness is in the range of 10 to 200 nm.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: January 6, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sheng Teng Hsu, Yoshi Ono
  • Patent number: 7475237
    Abstract: A system and method are provided for periodically servicing a channel in a timer used for controlling events. The method services a channel in a fixed periodic cycle, and reads a first control word loaded in the channel to determine a timer operation. Then, a first data word in the channel is managed in response to the determined operation. In one aspect, a clock signal is supplied with a fixed period. Then, servicing the channel in a fixed periodic cycle includes: establishing a cycle having a first number of clock signals; and, servicing the channel for a second number of clock signals each cycle. If the timer includes a plurality of channels, then each channel is serially serviced in a single cycle.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: January 6, 2009
    Assignee: Applied Micro Circuits Corporation
    Inventors: Brian F. Wilkie, Michael F. Wiles, Jay David Quirk
  • Patent number: 7471845
    Abstract: An image de-ringing filter system and method are provided. The method comprises: accepting image pixels; collecting data from a first group of pixels neighboring a test pixel; in response to the first group data, deciding if the test pixel includes image ringing artifacts; collecting data from a second group of pixels neighboring the test pixel; in response to the second group data, generating a filtered value (FV); and, replacing the test pixel actual value with FV. Typically, collecting data from the first and second group of pixels includes the performance of a mathematical operation. For example, a matrix may be defined for the multiplication of the first group of pixels. Values of pixels on a first side of the coordinate axis may be subtracted from pixels on a second side of the coordinate axis, opposite of the first side. Then, the difference is compared to a threshold.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: December 30, 2008
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Sachin Govind Deshpande
  • Patent number: 7470946
    Abstract: A triple-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is made from a bulk silicon (Si) substrate. A photodiode set including a first, second, and third photodiode are formed as a triple-junction structure in the Si substrate. A transistor set is connected to the photodiode set, and detects an independent output signal for each photodiode. Typically, the transistor set is formed in the top surface of the substrate. For example, the Si substrate may be a p-doped Si substrate, and the photodiode triple-junction structure includes the first photodiode forming a pn junction from an n+-doped region at the Si substrate top surface, to an underlying p-doped region. The second photodiode forms a pn junction from the p-doped region to an underlying n-well, and the third photodiode forms a pn junction from the n-well to the underlying p-doped Si substrate.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: December 30, 2008
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sheng Teng Hsu, Jong-Jan Lee