Abstract: A method of fabricating a grayscale mask includes preparing a silicon wafer; depositing a layer of Si3N4 directly on the silicon wafer; implanting H+ ions into the silicon wafer to form a defect layer; depositing a first layer of SiOxNy directly on the Si3N4 layer; depositing a layer of SRO directly on the first layer of SiOxNy; patterning and etching the SRO layer to form a microlens array in the SRO layer; depositing a second layer of SiOxNy on the SRO microlens array; CMP to planarize the second layer of SiOxNy; bonding and cleaving the planarized SiOxNyto a quartz plate to form a graymask reticle; etching to remove silicon from the bonded structure; etching to remove SiOxNy and Si3N4 from the bonded structure; and cleaning and drying the graymask reticle.

Abstract: A system and method are provided for framing messages in a data streams encoded with redundant information for transmission and recovering the messages at a receiver. The transmission method accepts an energy waveform representing N words at a first bit rate, encoded with redundant information, where each word includes P number of bits. The N words are transformed, creating N transcoded words, where each transcoded word includes Q number of bits, and where Q<P. The N transcoded words are mapped into M lanes in a buffer memory, where M>1 and each lane receives a frame of N/M transcoded words. A frame alignment marker is generated and mapped into each frame. Each frame is represented as an energy waveform that is transmitted on a corresponding physical lane at the first bit rate divided by M.

Abstract: A system and method are provided for negotiating a link data rate in a communication system using a plurality of data rates. In a system including a first device network-connected to a second device, auto-negotiation (AN) messages are mutually transmitted. The AN messages indicate rate information such as preferred data rate capabilities, if the device has a dual-rate capability, single data rate capabilities, or is capable of communicating over a plurality of physical medium lanes. If the AN messages are mutually transmitted, a negotiated link data rate is established. However, if one of the devices cannot send AN messages, the other device times-out, and a link data rate is established at the data rate transmitted by the device that is not AN-capable.

Abstract: A system and method are provided for converting multichannel serial data streams into packets. The method accepts a plurality of serial data streams in a corresponding plurality of channels. In a time domain multiplexed (TDM) fashion, groups with an undetermined number of data bits are packed from each data stream, into an associated channel segment queue, where each segment includes a predetermined number of bits. In a TDM fashion, segments are loaded into an associated channel payload queue, where each payload includes a predetermined number of segments. Once a payload is filled, an associated pointer is created in a pointer queue. The method selects a pointer from the pointer queue, creates a packet from the payload associated with the selected pointer, and transmits the packet via a packet interface. The packet overhead may include information stored in the pointer, a packet header, or a cyclic redundancy check (CRC) checksum.

Abstract: A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25.

Abstract: A system and method are provided for mapping information into Synchronous Payload Envelopes (SPEs). The method provides information bytes at a nominal system clock-based data rate, which is about equal to a system clock, but may be adjusted. An external clock has a rate approximately equal to the system clock rate. The method generates SPEs with identically-positioned information bytes, regardless of differences between the system and external clock rates. The SPEs are combined with Transport Overhead (TOH) and transmitted as a message frame at the external clock rate. SPEs are generated maintaining the positions of the information bytes within each SPE, without pointer adjustments, despite differences between the system and external clock rates. Expressed another way, message frames are generated with payload and TOH sections, and the information bytes are located exclusively in the payload sections. As a result, constant pointer values (e.g., H1/H2 or V1/V2) are maintained for all the SPEs.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: A system and method are provided for aggregating Multimedia over Coax Alliance (MoCA) Medium Access Control (MAC) frames. The method sends a Multiframe Reservation Request (MRR) requesting a transmission time slot, and receives a grant in response to the MRR. Subsequent to sending the MRR, a plurality of MoCA MAC frames are accepted and assembled into a physical layer (PHY) burst packet that is transmitted in the granted time slot. A method is also provided for bundling client data packets into a MoCA MAC frame. The method sends a Bundledpacket Reservation Request (BRR) requesting a transmission time slot, and receives a grant in response to the BRR. Subsequent to sending the BRR, a plurality of client data packets are accepted and concatenated into a bundled MoCA MAC frame. The bundled MoCA MAC frame is transmitted in a PHY packet in the granted time slot.

Abstract: An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x?4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.

Abstract: A dual-pixel full color CMOS imager comprises a two-photodiode stack including an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer at a first depth overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. A single photodiode including a bottom p doped layer overlies the substrate at a third depth. The third depth is less than, or equal to the first depth. A bottom n doped layer overlies the bottom p doped layer, a top p doped layer directly overlies the bottom n doped layer without an intervening layer, and a top n doped layer overlies the top p doped layer.

Abstract: A system and method are provided for jitter-free fractional division. The method accepts a first plurality of first signal phases, each phase having a first frequency. To make the division jitter-free, a phase is selected subsequent to deselecting a previous phase selection. The selected phase is divided by the integer N, supplying a second signal with a second frequency. Using the second signal as a clock, a first plurality of counts is triggered in series, and the counts are used to select a corresponding phase. The first signal may separate neighboring phases by 90 degrees. Then, for (N+0.25), a first count triggers a second count and selects the first phase, the second count triggers a third count and selects the second phase, the third count triggers a fourth count and selects the third phase, and the fourth count trigger the first count and selects the fourth phase.

Abstract: A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.

Abstract: A high-density plasma method is provided for forming a SiOXNY thin-film. The method provides a substrate and introduces a silicon (Si) precursor. A thin-film is deposited overlying the substrate, using a high density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, a SiOXNY thin-film is formed, where (X+Y<2 and Y>0). The SiOXNY thin-film can be stoichiometric or non-stoichiometric. The SiOXNY thin-film can be graded, meaning the values of X and Y vary with the thickness of the SiOXNY thin-film. Further, the process enables the in-situ deposition of a SiOXNY thin-film multilayer structure, where the different layers may be stoichiometric, non-stoichiometric, graded, and combinations of the above-mentioned types of SiOXNY thin-films.

Abstract: A method for smoothing an annealed surface uses a sub-resolution mask pattern. The method supplies a laser beam having a first wavelength and a mask with a first mask section having apertures with a first dimension and a second mask section with apertures having a second dimension, less than the first dimension. A laser beam having a first energy density is applied to a substrate region, melting a substrate region in response to the first energy density and crystallizing the substrate region. A diffracted laser beam is applied to the substrate region, smoothing the substrate region surface. Applying a diffracted laser beam to the substrate area may include applying a diffracted laser beam having a second energy density, less than the first energy density, to the substrate region.

Abstract: An array of crystalline silicon dies on a substrate and a method for yielding the array are provided. The method comprises: delineating an array of die areas on a crystalline semiconductor wafer; implanting the die areas with hydrogen ions; overlying the die areas with a layer of polymer to form, for each die, an aggregate including a die area first wafer layer; polymerically bonding an optically clear carrier to the die areas; thermally annealing the wafer to induce breakage in the wafer; forming, for each die, an aggregate wafer second layer with a thickness less than the die thickness; and, for each die, conformably attaching the aggregate wafer second layer to a substrate. The substrate can have an area of up to approximately two square meters and the wafer second layer can have a thickness of greater than and equal to approximately 20 nanometers.

Abstract: A thin-film transistor (TFT) with a multilayer gate insulator is provided, along with a method for forming the same. The method comprises: forming a channel, first source/drain (S/D) region, and a second S/D region in a Silicon (Si) active layer; using a high-density plasma (HDP) source, growing a first layer of Silicon oxide (SiOx) from the Si active layer, to a first thickness, where x is less than, or equal to 2; depositing a second layer of SiOx having a second thickness, greater than the first thickness, overlying the first layer of SiOx; using the HDP source, additionally oxidizing the second layer of SiOx, wherein the first and second SiOx layers form a gate insulator; and, forming a gate electrode adjacent the gate insulator. In one aspect, the second Si oxide layer is deposited using a plasma-enhanced chemical vapor deposition (PECVD) process with tetraethylorthosilicate (TEOS) precursors.

Abstract: A piezo-TFT cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method comprises: providing a substrate, such as glass for example; forming thin-films overlying the substrate; forming a thin-film cantilever beam; and simultaneously forming a TFT within the cantilever beam. The TFT is can be formed least partially overlying a cantilever beam top surface, at least partially overlying a cantilever beam bottom surface, or embedded within the cantilever beam. In one example, forming thin-films on the substrate includes: selectively forming a first layer with a first stress level; selectively forming a first active Si region overlying the first layer; and selectively forming a second layer overlying the first layer with a second stress level. The thin-film cantilever beam is formed from the first and second layers, while the TFT source/drain (S/D) and channel regions are formed from the first active Si region.

Abstract: A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.

Abstract: A system and method are provided for controlling the duty cycle and frequency of a digitally generated clock. The method accepts a first clock signal having a fixed first frequency. A frequency control word with a first pattern is loaded into a first plurality of serially-connected registers. A duty cycle control word with a second pattern is loaded into a second plurality of serially-connected registers. A register clock signal is generated in response to the first clock and the first pattern. Then, a digital clock signal is generated having a frequency and duty cycle responsive to the register clock signal and the second pattern.

Abstract: A system and method have been provided for pushing cacheable control messages to a processor. The method accepts a first control message, identified as cacheable and addressed to a processor, from a peripheral device. The first control message is allocated into a cache that is associated with the processor, but not associated with the peripheral device. In response to a read-prompt the processor reads the first control message directly from the cache. The read-prompt can be a hardware interrupt generated by the peripheral device referencing the first control message. For example, the peripheral may determine that the first control message has been allocated into the cache and generate a hardware interrupt associated with the first control message. Then, the processor reads the first control message in response to the hardware interrupt read-prompt. Alternately, the read-prompt can be the processor polling the cache for pending control messages.