Abstract: A stored resource overlay system and method are presented. The method comprises: at a MFP, accepting a document, either in tangible form to be copied, or as an electronically formatted scan job; accessing a resource file stored in permanent storage; converting the resource file into an image; merging the image with the document; and, creating a merged document in an electronic format. The saved resource file may represent an image type such as a logo, background, signature, border, graphic, picture, or overlay for example. After accepting the document, it is converted to a rasterized data first image. Likewise, the image, converted from resource file in permanent storage, is supplied as a rasterized data second image. Then, merging the image with the document includes: adding the first image to the second image; and, generating a rasterized data third image. The resource file in permanent storage may be saved in a PDL format for example.

Abstract: A photovoltaic (PV) structure is provided, along with a method for forming a PV structure with a conductive nanowire array electrode. The method comprises: forming a bottom electrode with conductive nanowires; forming a first semiconductor layer of a first dopant type (i.e., n-type) overlying the nanowires; forming a second semiconductor layer of a second dopant type, opposite of the first dopant type (i.e., p-type), overlying the first semiconductor layer; and, forming a top electrode overlying the second semiconductor layer. The first and second semiconductor layers can be a material such as a conductive polymer, a conjugated polymer with a fullerene derivative, and inorganic materials such as CdSe, CdS, Titania, or ZnO. The conductive nanowires can be a material such as IrO2, In2O3, SnO2, or indium tin oxide (ITO).

Abstract: A system and method are provided for selecting loss of signal (LOS) criteria in a serial communications receiver. The method receives a serial stream of digital data and selects LOS criteria. The serial stream of digital data is compared to the selected LOS criteria. In response to the serial stream of digital data failing to meet the selected LOS criteria, a LOS signal is generated. Some examples of the LOS criteria that might be selected include: a “signal detect” signal received from the source transmitting the serial stream of digital data, a run length test, a signal strength (voltage amplitude) test, harmonic band detection test, and a received data clock test. In one aspect, selecting LOS criteria includes selecting combinations of the above-mentioned LOS criteria, so that the LOS signal is generated in response to failing to meet the combination of selected LOS criteria.

Abstract: A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method provides a substrate; forms an MSM bottom electrode overlying the substrate; forms a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forms an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

Abstract: A system and method are provided for measuring the amplitude of a received signal. The method receives an analog input signal, and compares a peak value of the analog input signal to a threshold level. Threshold transition data is generated, and the threshold level is adjusted in response to the transition data. The above-mentioned processes of comparing, generating, and adjusting are reiterated until the threshold level is about equal to the analog input signal peak value. As a result, a measurement of the analog input signal peak value is supplied. In one aspect, threshold transition data is converted into a digital value. Then, the measurement of the analog input signal peak value uses the digital value to represent the analog input signal peak value. Further, the digital value is converted into an analog voltage as feedback, and the analog voltage is used as the threshold level.

Abstract: A silicon (Si)-on-insulator (SOI) high voltage transistor with a body ground is provided with an associated fabrication process. The method provides a SOI substrate with a buried oxide (BOX) layer and a Si top layer having a first thickness and a second thickness, greater than the first thickness. A body ground is formed in the second thickness of Si top layer overlying the BOX layer. A control channel is formed in the first thickness of the Si top layer. A control gate is formed overlying the control channel. An auxiliary channel is formed in the second thickness of Si top layer partially overlying the body ground and extending into the first thickness of the Si top layer. An auxiliary gate is formed overlying the auxiliary channel. A pn junction is formed in the second thickness of Si top layer between the auxiliary channel and the body ground.

Abstract: A process of lateral crystallization is provided for increasing the lateral growth length (LGL). A localized region of the substrate is heated for a short period of time. While the localized region of the substrate is still heated, a silicon film overlying the substrate is irradiated to anneal the silicon film to crystallize a portion of the silicon film in thermal contact with the heated substrate region. A CO2 laser may be used as a heat source to heat the substrate, while a UV laser or a visible spectrum laser is used to irradiate and crystallize the film.

Abstract: An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p?/p/p?/p layered structure.

Abstract: A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.

Abstract: A thermal electric (TE) binary NAND gate logic circuit is provided with a method for NAND logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NAND logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage.

Abstract: A system and method are provided for calibrating orthogonal polarity in a multichannel optical transport network (OTN) receiver. The method accepts a composite signal and separates the polarization of the signal into a pair of 2n-phase shift keying (2n-PSK) modulated input signals via Ix and Qx optical signal paths, where n?1. Likewise, a pair of 2p-PSK modulated input signals are accepted via Iy and Qy optical signal paths where p?1. Polarization-adjusted I?x, Q?x, I?y, and Q?y signals are generated. An average magnitude is compared to either 2×the absolute magnitude of (I?x and Q?x), or 2×the absolute magnitude of (I?y and Q?y). The average magnitude value can be used that is either 2×(a predetermined peak signal amplitude), or the sum of the absolute magnitudes of (I?x and Q?x) and (I?y and Q?y). The polarization-adjusted I?x, Q?x, I?y, and Q?y signals are modified until the magnitude comparison is about zero.

Abstract: A thermal expansion interface between silicon (Si) and gallium nitride (GaN) films using multiple buffer layers of aluminum compounds has been provided, along with an associated fabrication method. The method provides a (111) Si substrate and deposits a first layer of AlN overlying the substrate by heating the substrate to a relatively high temperature of 1000 to 1200° C. A second layer of AlN is deposited overlying the first layer of AlN at a lower temperature of 500 to 800° C. A third layer of AlN is deposited overlying the second layer of AlN by heating the substrate to the higher temperature range. Then, a grading Al1-XGaXN layer is formed overlying the third layer of AlN, where 0<X<1, followed by a fixed composition Al1-XGaXN layer overlying the first grading Al1-XGaXN layer. An epitaxial GaN layer can then be grown overlying the fixed composition Al1-XGaXN layer.

Abstract: A method is provided for fabricating a silicon (Si)-on-insulator (SOI) double-diffused metal oxide semiconductor transistor (DMOST) with a stepped channel thickness. The method provides a SOI substrate with a Si top layer having a surface. A thinned area of the Si top layer is formed, and a source region is formed in the thinned Si top layer area. The drain region is formed in an un-thinned area of the Si top layer. The channel has a first thickness adjacent the source region with first-type dopant, and a second thickness, greater than the first thickness, adjacent the drain region. The channel also has a sloped thickness between the first and second thicknesses. The second and sloped thicknesses have a second-type dopant, opposite of the first-type dopant. A stepped gate overlies the channel.

Abstract: A ZnO film with a C-axis preference is provided with a corresponding fabrication method. The method includes: forming a substrate; forming an amorphous Al2O3 film overlying the substrate; and, forming a ZnO film overlying the Al2O3 film at a substrate temperature of about 170° C., having a C-axis preference responsive to the adjacent Al2O3 film. The substrate can be a material such as Silicon (Si) (100), Si (111), Si (110), quartz, glass, plastic, or zirconia. The Al2O3 film can be deposited using a chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering process. Typically, the Al2O3 layer has a thickness in the range of about 3 to 15 nanometers (nm). The step of forming the ZnO film having a C-axis preference typically means that the ZnO film has a (002) peak at least 5 times greater than the (100) peak, as measured by X-ray diffraction (XRD).

Abstract: A device and a fabrication method are provided for an EL device with a nanotip-contoured phosphor layer. The method comprises: forming a bottom electrode with nanotips; forming a phosphor layer overlying the bottom electrode, having irregularly-shaped top and bottom surfaces; and, forming a top electrode overlying the phosphor layer. The bottom electrode top surface has a nanotip contour, and the phosphor layer irregularly-shaped top and bottom surfaces have contours approximately matching the bottom electrode top surface nanotip contour. In one aspect, a contoured bottom dielectric is interposed between the bottom electrode and the phosphor layer, having top and bottoms surfaces with contours approximately matching the nanotip contour. Likewise, a top dielectric may be interposed between the top electrode and the phosphor layer, having a bottom surface with a contour approximately matching the contour of phosphor layer top surface.

Abstract: A system and method are provided for a sampled accumulation method that maps information into Synchronous Payload Envelopes (SPEs). The method buffers data from a plurality of tributaries, and sequentially stores buffer-fill information for each tributary in a first memory, at a rate of up to one tributary per system clock (Fsys) cycle. A stored accumulation of buffer-fill information for each tributary is updated at a sample rate frequency (Fsample), where Fsample?Fsys. The stored accumulation of buffer-fill information is used to calculate stuff bit opportunities for each tributary. As a result, the rate of data being mapped into outgoing tributaries is regulated, and the outgoing mapped tributaries are combined in a SPE.

Abstract: A method is provided for forming a rare earth element-doped silicon oxide (SiO2) precursor with nanocrystalline (nc) Si particles. In one aspect the method comprises: mixing Si particles into a first organic solvent, forming a first solution with a first boiling point; filtering the first solution to remove large Si particles; mixing a second organic solvent having a second boiling point, higher than the first boiling point, to the filtered first solution; and, fractionally distilling, forming a second solution of nc Si particles. The Si particles are formed by immersing a Si wafer into a third solution including hydrofluoric (HF) acid and alcohol, applying an electric bias, and forming a porous Si layer overlying the Si wafer. Then, the Si particles are mixed into the organic solvent by depositing the Si wafer into the first organic solvent, and ultrasonically removing the porous Si layer from the Si wafer.

Abstract: A system and method are provided for transporting Plesiochronous Digital Hierarchy (PDH) tributaries. The method accepts a plurality of PDH tributaries; generates a serial data stream of interleaved PDH tributaries; generates a serial control stream of signals for recovering the PDH tributaries; and, generates a clock signal for timing the data and control streams. The serial data stream of interleaved PDH tributaries is loaded into the payload of a data frame structure. Likewise, the serial control stream is loaded into the payload of a control frame structure. The data bytes of the serial data stream and the control bytes of the serial control stream are both transmitted at the same data rate. That is, there is a control byte generated for each data byte. Thus, the control bytes in the control frame structure are aligned with corresponding data bytes in the data frame structure.

Abstract: A system and method are provided for processing a document. The method comprises: marking an area of a document, using at least one predetermined markup symbol; identifying a markup symbol; using the identified markup symbol to locate the document area; determining characters in the document area; and, processing the determined characters. Fields that can be processed include title, keywords, author, signature, document name, category, subject, or document status, to name but a few examples. In some aspects, marking an area of a document, using at least one predetermined markup symbol includes: electronically marking using a medium such as a touchscreen, pressure pad, or a mouse. Alternately, the paper document can be physically marked (with a pen or pencil) before scanning. Typically, marking an area of a document includes forming a markup character proximate to an enclosing figure. A wide range of markup characters can be defined cross-referenced to document processes.

Abstract: An integrated MEMS package and associated packaging method are provided. The method includes: forming an electrical circuit, electrically connected to the first substrate; integrating a MEMS device on a first substrate region, electrically connected to the first substrate; providing a second substrate overlying the first substrate; and, forming a wall along the first region boundaries, between the first and second substrate. In one aspect, the electrical circuit is formed using thin-film processes; and, wherein integrating the MEMS device on the first substrate region includes forming the MEMS using thin-film processes, simultaneous with the formation of the electrical device. Alternately, the MEMS device is formed in a separate process, attached to the first substrate, and electrical interconnections are formed to the first substrate using thin-film processes.