Abstract: A graphics pipeline including a rasterizing stage producing diffuse color values; a plurality of texture stages producing texture values defining a particular texture; a combiner stage for combining four of a plurality of selectable input values including diffuse color values, texture values furnished by a plurality of texture stages, and proportions for combination of the selectable input values; the combiner stage being capable of providing a result equivalent to a sum of products of any two sets of input values, and a product of two input values.

Abstract: A process for the formation of metal salicide regions and metal salicide exclusion regions in an integrated circuit (IC) that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process, an IC structure is first provided. The IC structure includes a plurality of MOS transistor structures with exposed silicon surfaces, such as source regions, drain regions and polysilicon gates. A metal layer (e.g., cobalt, titanium, tantalum, nickel or molybdenum) is then deposited over the IC structure, followed by the formation of a photoresist masking layer on those MOS transistor structures where metal salicide regions are to be formed. The metal layer from those MOS transistor structures where metal salicide exclusion regions are to be formed is then removed, followed by stripping of the photoresist masking layer from those MOS transistor structures where metal salicide regions are to be formed.

Abstract: A differential amplifier and method including a differential pair of input MOS transistors coupled to a common tail current source and a pair of MOS load transistors, with the amplifier outputs being disposed intermediate the input and load transistors. Biasing circuitry is included to maintain the load transistors in the linear region of operation. Reset transistors can be used to periodically reset the amplifier by connecting the outputs directly to the inputs.

Abstract: A bookbinding structure and method. The bookbinding structure is, used to bind pages together in existing, commercially available binding machines. The bookbinding structure has a heat activated adhesive matrix for binding the pages. To attach a wrap-around book cover once the pages have been bound with the bookbinding structure, an adhesive on the outer surface of the bookbinding structure may be exposed by removing a release liner covering the adhesive. The book cover may then be adhered to the exposed adhesive either by a heat method or by applying pressure over the adhesive, depending on the particular type of adhesive of the bookbinding structure. The book cover may be printed with information and/or graphics prior to being wrapped around the pages of the book.

Abstract: An apparatus according to a preferred embodiment of the present invention includes two memories each storing different octants of a sine (or cosine) waveform. The sine and cosine waveforms may be concurrently generated by alternately accessing each memory in succession. It is unnecessary to access one memory concurrently, so that both waveforms may be concurrently generated without requiring either two accesses to the same memory or a doubled memory size.

Abstract: A comparator circuit having a first state and a second state, a threshold potential for transition from the first state to the second state, another threshold potential for transition from the second state to the first state, and hysteresis characteristics that are independent of process, temperature, and supply voltage variations. Preferably, the threshold potentials and hysteresis characteristics depend only on a reference potential and on ratios of resistances of pairs of resistors.

Abstract: An amplifier input stage having a constant input gm and including first and second differential transistor pair so as to provide operation with inputs at or near the upper and lower power supply rails. A comparator circuit operates to control which of the transistor pair is active based upon the relative magnitudes of the amplifier input stage inputs and a reference voltage.

Abstract: A method and apparatus for pressurizing the right atrium or right ventricle of a beating heart during surgery to assist cardiac function. The apparatus has an intake tube for insertion in the inferior or superior vena cava, a return tube for insertion in the right atrium or right ventricle, and a pump (e.g., a peristaltic pump). In operation, blood is pumped from the vena cava into an intake port of the intake tube, from the intake tube through the pump to the return tube, and from the return tube to the right atrium or right ventricle. Optionally, a balloon mounted around the intake tube's distal end is inflated to center the intake port in the vena cava and provide a pressure bulkhead. The pump preferably pumps blood in one direction from an input port to an output port.

Abstract: A graphics accelerator pipeline including a rasterizer stage, a texture stage, and a combiner stage capable of producing realistic output images by mapping irregular textures to surfaces.

Abstract: Process for the formation of a polysilicon layer with a controlled, small silicon grain size that includes first providing a semiconductor substrate (such as a silicon wafer), followed by the formation of a silicon dioxide layer (such as a gate silicon dioxide layer) on the semiconductor substrate. Next, an amorphous silicon layer is deposited on the silicon dioxide layer. The amorphous silicon layer can be deposited using LPCVD at a temperature in the range of 520° C. to 560° C. and a pressure in the range of 150 mTorr to 250 mTorr. Next, a plurality of silicon crystallites are formed in the amorphous silicon layer by subjecting it to a first RTA cycle at a temperature in the range of 750° C. to 850° C. for a time period of 30 seconds to 90 seconds and a temperature ramp rate of at least 50° C. per second.

Abstract: A networked computer includes a system controller having a network interface. When the networked computer enters a reduced-power state, the network interface receives frame data. The network interface filters the frame data and saves selected frame data to a memory. The memory provides the frame data to the system controller.

Abstract: An integrated circuit including a plurality of connectors for communicating with circuitry within the integrated circuit, a plurality of input/output pads for connecting to external circuitry, a plurality of multiplexors joined to the connectors and the input/output pads, means for providing an external control signal for each multiplexor for joining the plurality of connectors for communicating with circuitry within the integrated circuit to correct input/output pads for connecting to external circuitry for operating the integrated circuit.

Abstract: An on-time signal generation circuit for use in a switching DC-to-DC converter, a switching DC-to-DC converter including such a circuit, and a method for generating an on-time signal which is a binary pulse train comprising pulses TON, where the width of each pulse TON is equal to TOSC (Vout/Vin), where TOSC, Vin, and Vout are, respectively, the switching period and the input potential of a DC-to-DC converter, and a control potential. The control potential Vout is one of the output potential of the DC-to-DC converter and a DC potential proportional to a desired level of such output potential. The on-time signal generation circuit includes a comparator, a ramp generator with an output coupled to one input of the comparator, and an amplifier with an output coupled to the other input of the comparator. The ramp generator generates a periodic ramped potential having peak level kVin and period Tosc.

Abstract: A direct memory access (DMA) circuit which is physically positioned with an input/output device, the DMA circuit storing a first reference value pointing to a data structure which describes a buffer portion of system memory in which data is stored for transfer to the I/O device, a value determining a position within the buffer portion of system memory beginning at which a next sequence of data is to be placed, and a value determining a position within the buffer portion of system memory from which a next sequences of data is to be copied to the I/O device, the DMA circuit including circuitry for reading data from the buffer portion of system memory beginning at the position from which a next sequences of data is to be copied and for writing the data read to the I/O device.

Abstract: A graphics accelerator including an address remapping memory which straddles slow address spaces and fast address spaces.

Abstract: A voltage stress testable embedded dual capacitor structure for use in an integrated circuit (IC). The voltage stress testable embedded dual capacitor structure includes a semiconductor substrate with an electrically insulating base layer thereon, a first embedded dual capacitor and a second embedded dual capacitor connected in series and disposed on the electrically insulating base layer, and a probe pad. The probe pad is electrically connected directly to the first and second embedded dual capacitors at a location therebetween (e.g. by being connected to an electrically conductive top plate of the second embedded dual capacitor). The voltage stress testable embedded dual capacitor structure can be voltage stress tested using an applied voltage high enough to assure the reliability of the first and second embedded dual capacitors, without exposing other electronic devices in the IC to a damaging level of voltage. Also provided is a process for voltage stress testing embedded dual capacitors.

Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.

Abstract: A driver circuit implemented in an integrated circuit for driving an output node, typically connected to another integrated circuit. The driver circuit includes a control section which produces a digital control output indicative of the state of the process used to manufacture the integrated circuit. One or more driver sections, each connected to an output node of the integrated circuit, receive the digital control output and use the output to control the state of a transistor array connected between the associated output node and circuit common. The transistor array includes an offset transistor having a channel width to channel length ratio Wo/Lo and a multiplicity of adjust transistors, designated first through N, having respective channel width to channel length ratios (Wa/La)N approximately equal to (Wo/Lo) (1+&Dgr;)N where &Dgr; is a fixed weighted value less than one, such as 0.1.

Abstract: A DC-to-DC converter having multiple power channels and a switching controller which generates a pulse-width modulated control signal for each power channel, and a switching controller for use in (and a method for generating power switch control signals for) such a converter. The control signals are generated in response to trigger signal trains generated by trigger channels. The trigger channels rotate relative to the power channels so that the control signals are generated in response to a sequence of trigger channel states. In some embodiments, the controller has one control signal channel and one trigger channel for each power channel. In other embodiments, there are N power channels, N control signal channels, and M reset channels (each for generating a trigger signal train), where M is an integer greater than N. The extra channel or channels is used for preventing rotation errors which would otherwise delay opening of the closed power switches.

Abstract: A buffer circuit having voltage clamping capabilities. The buffer circuit includes an input transistor having a gate which receives the input voltage to be buffered and a source connected to a current source. A first clamping transistor has a source connected to the source of the input transistor and a gate which receives a lower clamping voltage. A second clamping transistor is connected intermediate the input transistor and a power supply rail and has a gate for receiving an upper clamping voltage. In one embodiment, the output of the buffer is at the source of the input transistor. In another embodiment, the buffer is implemented as a differential amplifier with the input, first clamping and second clamping transistors being on an input half of the amplifier and the output of the buffer being at the output half.