Abstract: A system and signal processing method, in which at least two processors have prioritized, shared access to one or more devices connected along a bus. In preferred embodiments, a fast processor is connected along a first bus, a slow processor and shared device are connected along a second bus, and a communication device is connected between the buses. The communication device is configured to provide the fast processor continuous access to the shared device (in response to grant of an access request by the fast processor) for a limited time that is longer than the time required for a single word transfer, but the slow processor must contend with the fast processor for access to the shared device each time after the slow processor completes a word transfer. Preferably, the communication device provides the fast processor continuous access to the shared device for up to a maximum number of word transfers in response to grant of one access request by the fast processor.

Abstract: An apparatus for and method of generating a signal for equalizing propagation delay among parts of a transceiver are disclosed. The parts each have a plurality of channels, and each channel is configured to receive the signal. The apparatus includes a master circuit and a dummy channel circuit. The master circuit is configured to receive and lock to a reference clock signal, and in accordance therewith generate a reference delay signal and an adjusted clock signal. The dummy channel circuit is configured to receive the adjusted clock signal, the reference delay signal and a dummy data signal, and in accordance therewith generate an intermediate data signal, the dummy data signal and one or more control signals. The control signals correspond to a delay between the adjusted clock signal and the intermediate data signal. In this manner a uniform delay may be provided to all parts and channels.

Abstract: A band gap circuit that may be implemented in a standard CMOS process including a pair of parasitic vertical PNP transistors operating at a different current density. The PNP transistors have common collectors and common bases and produce a difference in base-emitter voltages which is developed across a resistor so as to produce a current having a positive temperature coefficient. The current is used to produce a positive temperature coefficient voltage which is combined with another voltage having a negative temperature coefficient to produce a band gap reference voltage. A bias voltage is applied between the base and collector of each of the PNP transistors, typically on the order of 500 millivolts. This causes the emitters of the PNP transistors to be at a voltage which can be sensed by an error amplifier implemented with standard N type MOS input transistors while maintaining a capability of operating using a relatively low power supply voltage.

Abstract: A networked computer includes a system controller having a network interface. When the networked computer enters a reduced-power state, the network interface receives frame data. The network interface filters the frame data and saves selected frame data to a memory. The memory provides the frame data to the system controller.

Abstract: An apparatus for and method of generating a signal having a programmable period and a programmable duty cycle. The apparatus includes an update sequencer circuit. The update sequencer circuit is configured to detect an updated period value and an updated duty cycle value, and to receive a period match signal, and in accordance therewith selectively generate a period write signal and a duty cycle write signal. A storage element is configured to receive the updated period value, the updated duty cycle value, the period write signal, and the duty cycle write signal, and in accordance therewith replace a period value with the updated period value and a duty cycle value with the updated duty cycle value. The update sequencer circuit eliminates the requirement for associated software to have a polling loop or an interrupt.

Abstract: An integrated circuit including a resistor that at least partially overlies a first tub of semiconductor material of a first polarity, where the first tub is formed in a second tub of semiconductor material having the opposite polarity, and the second tub is formed in a semiconductor substrate having the first polarity. The second tub forms the base of a vertical bipolar transistor, the first tub forms the emitter of the transistor, and the substrate forms the collector of such transistor. Where the vertical transistor is a PNP transistor, the first tub is the emitter and consists of P-type semiconductor material, the second tub is the base, and the substrate is the collector. Preferably, the resistor is a strip of polysilicon or a set of multiple, series-connected polysilicon segments. Typically, the integrated circuit is an amplifier and the resistor is a gain-setting resistor.

Abstract: A comparator circuit for comparing a differential input signal to a reference signal. A differential MOS transistor pair is provided having respective gates for receiving the positive and negative components of the differential input signal. A tail current source is coupled to the common sources of the transistor pair, with the current magnitude being related to the reference signal magnitude. The first and second transistors are made differently, typically by making the sizes different, so that the gate-source voltages differ when the transistor currents are equal. A comparator stage provides a digital output which changes state when the transistor currents are equal, with the difference in gate-source voltage representing the comparator trip voltage, a trip voltage related to the magnitude of the reference signal.

Abstract: A bookbinding system and method of binding books including a cover/spine assembly having a relatively rigid cover section with a length and width at least as great as that of the stack of sheets to be bound and a spine section having a width greater than the height of the stack. The cover/spine assembly and the spine section are secured together along the length of the cover section so that the spine section can be folded along a first edge with respect to the cover/spine assembly. A heat activated matrix is disposed on the spine section including a central adhesive band and an outer band disposed between the central adhesive band and a second edge of the spine section. Binding is carried out by placing the stack over the cover section and folding the spine section over the edge of the stack. Preferably a second relatively rigid cover section is placed on top of the stack so that the outer adhesive band on the spine section will extend over second cover section.

Abstract: A vibration resistant test module for use with semiconductor device test apparatus that includes a test module top plate, a test module bottom plate and a plurality of spring-and-wire assemblies. The test module top and bottom plates each have a plurality of openings extending between their upper and lower surfaces. Each of the spring-and-wire assemblies includes an electrically conducting wire with a top wire end and a bottom wire end, a top electrically conducting spring connector attached to the top wire end, and a bottom electrically conducting spring connector attached to the bottom wire end. The spring-and-wire assemblies are threaded through separate openings in the test module top and bottom plates such that the top electrically conducting spring connectors extend above the upper surface of the test module top plate, while the bottom electrically conducting spring connectors extend below the lower surface of the test module bottom plate.

Abstract: An amplifier circuit which operates to level shift a differential input signal and to provide a single-ended output. The circuit includes a level shifting stage which defines two current paths, with one path being controlled by one component of the differential input and the other path being controlled by the other component. A transistor is connected in series with each of the current paths. A driver stage coupled to the first and second current paths provides first and second driver outputs indicative of voltage levels on the first and second current paths. A common mode feedback circuit operates to alter current flow in the current paths in response to the first and second driver outputs. An output stage includes one output transistor coupled between one power supply rail and an amplifier output and another transistor output transistor coupled between a second power supply rail and the amplifier output.

Abstract: An apparatus for and method of testing similar circuit blocks with test signals. The apparatus includes a first logic bus circuit, a second logic bus circuit, and a selector circuit. The first logic bus circuit is used to serially test the similar circuit blocks. The second logic bus circuit is used to concurrently test the similar circuit blocks. The selector circuit indicates an error with a high impedance circuit state. The number of output pins is dependent upon the number of test signals, not the number of similar circuit blocks. This allows the apparatus to be scalable to any number of similar circuit blocks without increasing the required number of output pins.

Abstract: A switching DC-to-DC converter having at least one power channel including an inductor and a controller which generates at least one power switch control signal for at least one power switch of each power channel. The converter is configured to operate in a continuous mode when the inductor current remains above zero, to enter a discontinuous pulse skipping mode of operation when the inductor current falls to zero (which occurs when the load current is below a threshold value), and to leave the discontinuous pulse skipping mode and resume continuous mode operation when the inductor current rises above zero.

Abstract: A transistor saturation control circuit for controlling saturation of a PNP transistor. The control circuit includes current sense circuitry which produces a control output in response to a change in current of an N well associated with the PNP transistor. Base drive control circuitry operates to limit base drive to the PNP transistor in response to the control output.

Abstract: An integrated circuit having at least one segmented array of switches, wherein the root node of each segmented array of switches is a node whose potential varies with time during operation. Each segmented switch array includes switches connected between nodes having a tree structure. The nodes include the root node and additional nodes of at least two different degrees relative to the root node. By providing a segmented array (rather than a non-segmented array) of switches at a node, the total load capacitance (including parasitic capacitance) at the node is reduced in accordance with the invention. In preferred embodiments, the invention is an analog integrated circuit having a first node at which the potential varies rapidly, and a segmented array of switches whose root node is the first node. Another aspect of the invention is a method for designing an integrated circuit to have reduced load capacitance (e.g.

Abstract: A current generator circuit having an output current with a stable absolute magnitude and which is proportional to a temperature of about T0.5 Kelvin. An MOS transistor operating in the linear region produces a drain-source current related to the output current and is biased with a drain-source voltage related to the difference between the base-emitter voltage of a pair of bipolar transistors operating at different current densities. The temperature coefficient of the output current is ideal for biasing an amplifier circuit so as to maintain a minimum settling time over a specified temperature range.

Abstract: An amplifier output stage including a PNP transistor having an emitter coupled to a power rail and a collector coupled to an amplifier output. The PNP transistor is driven by an NPN transistor having a collector coupled to the base of the PNP transistor. A bias circuit produces a base-emitter voltage across the PNP transistor so that the PNP transistor will conduct a desired quiescent current. The bias circuit has an effective output impedance which is sufficiently large to form a pole in combination with a frequency compensation capacitor coupled to the collector of the PNP transistor, with the pole being located at a frequency beyond the unity-gain frequency of the amplifier.

Abstract: A cascode amplifier integrated circuit (IC) with a relatively fast transient fall response (i.e., short transient fall response time) and, therefore, relatively fast operation. The cascode amplifier IC includes a bias input terminal configured to receive a bias potential Vb, a power supply input terminal configured to receive a power supply voltage Vcc, an input signal terminal configured to receive an input voltage signal Vin, and an output signal terminal. The cascode amplifier IC also includes a gain stage circuit with a plurality of interconnected bipolar transistors and an output buffer stage circuit configured. The cascode amplifier integrated circuit further includes a discharge circuit configured to discharge stray capacitance at a node of the output buffer stage circuit.

Abstract: An integrated circuit including one or more power devices, and circuitry which reliably (and independently) shuts down each power device that is detected to be in an undesired operating condition (e.g., one or both of an overcurrent condition and an overvoltage condition) that causes a thermal fault, but which does not shut down any power device that is not in such undesired operating condition. In typical implementations in which the integrated circuit has multiple power devices and an overvoltage detection circuit for each power device, the integrated circuit includes a thermal fault detection circuit and logic circuitry which receives the output of the thermal fault detection circuit and each overvoltage detection circuit. The logic circuitry generates signals which shut down appropriate ones of the power devices in response to the thermal fault detection and overvoltage detection signals it receives.

Abstract: An active pixel sensor cell array including a XDR reset signal generation circuit configured to generate XDR reset signals having user-selected levels, and an XDR reset signal generation circuit for use with such an array. The XDR reset signal generation circuit includes a digital-to-analog converter (DAC) coupled to receive control bits which determine the level and time of assertion of each XDR reset signal, and a level shifting circuit coupled to the output of the DAC. In response to the control bits (typically a sequence of multi-bit words), the circuit asserts a time-varying XDR reset potential. The XDR reset potential's amplitude as function of time (during each integration period) determines the breakpoints of each cell's response curve.

Abstract: A circuit for generating a ramped voltage having controlled maximum amplitude (e.g., for use in a switching controller), and a method for generating such a ramped voltage without use of a comparator. The ramped voltage is a voltage developed across a periodically charged and discharged capacitor, or optionally a level-shifted version of such voltage. Preferably, a ring oscillator generates a clock signal (without use of a comparator) for use in controlling the periodic charging and discharging of the capacitor, and a feedback loop generates a supplemental charging current for the capacitor in response to feedback indicative of the ramped output voltage.