Patents Represented by Attorney Girard & Equitz LLP
  • Patent number: 6233165
    Abstract: A power supply arrangement including a transformer and a switching element coupled to a primary winding of the transformer and a power supply. The power supply includes a capacitor having a first terminal coupled to a junction of the primary winding and the switching element and a first diode coupled between the capacitor and an output node. The power supply further includes a discharge element, such as a resistor or a diode, coupled between the junction of the first diode and the capacitor and a power supply common. A voltage regulator, such as a Zener diode, is connected to the output node to produce a regulated voltage powered by the voltage applied to the transformer primary winding, with the regulated voltage being used to power the control circuitry.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: May 15, 2001
    Assignee: ASIC Advantage, Inc.
    Inventors: Pierre R. Irissou, Hans R. Camenzind
  • Patent number: 6229293
    Abstract: A DC-to-DC converter which includes a current mode switching controller or regulator chip (which includes an oscillator producing a ramped voltage which periodically increases at a fixed ramp rate), circuitry including a current sense resistor external to the integrated circuit controller, and ramp adjustment circuitry (including at least one element external to the integrated circuit controller) which sets the effective ramp rate of the oscillator's ramped voltage. The external element of the ramp adjustment circuitry can be a resistor or a capacitor, or circuitry comprising both a resistor and capacitor.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: May 8, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Douglas Robert Farrenkopf
  • Patent number: 6225666
    Abstract: A low stress active area silicon island structure with a reduced susceptibility to gate polysilicon layer “wraparound” and stringer formation during subsequent semiconductor manufacturing. The structure includes a semiconductor substrate (e.g. a silicon wafer) with an electrical insulation layer (e.g. a SiO2 layer) thereon. The electrical insulation layer has an active area opening extending from its surface to the surface of the underlying semiconductor substrate. The structure also includes an active area silicon island filling the active area opening. A cross-section of the active area silicon island perpendicular to the surface of the semiconductor substrate has a non-rectangular profile, for example a “wineglass” profile. A process for the formation of a low stress active area silicon island structure includes first providing a semiconductor substrate, followed by forming an electrical insulation layer thereon.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: May 1, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Kamesh V. Gadepally