Abstract: A method for performing an elevated temperature process on an integrated device whereby a magnetic field is used to maintain the alignment of magnetic domains in magnetically sensitive materials.

Abstract: A power distribution system for a semiconductor die includes bonding pads located adjacent to and connected to power busses with connections between the bonding pads providing a parallel path for current. Connections may be provided by stitch bonds, by conductors within a substrate or by other means.

Abstract: Chip stacking and capacitor mounting arrangement including a planar spacer separating a first die and a second die. A conductive spacer provides for backside chip grounding in one application and provides for capacitor mounting in another application.

Abstract: A shielding apparatus for an electronic component includes a first insulative encapsulant surrounding at least a portion of the component and a second encapsulant surrounding said first encapsulant and having conductive particles dispersed therein for absorbing ionizing radiation.

Abstract: A delay element including a stack of p-channel transistors connected in series and a stack of n-channel transistors connected in series with the source of the top p-channel transistor connected to a positive voltage and the source of the bottom n-channel transistor connected to ground. The drain of each n-channel transistor is connected to the drain of a corresponding one of the p-channel transistors and all gates are interconnected and serve as the input to the delay element. The output of the delay element can be any one of the drain connections.

Abstract: A method and apparatus for sensing a desired component of a magnetic field using an isotropic magnetoresistive material. This is preferably accomplished by providing a bias field that is parallel to the desired component of the applied magnetic field. The bias field is applied in a first direction relative to a first set of magnetoresistive sensor elements, and in an opposite direction relative to a second set of magnetoresistive sensor elements. In this configuration, the desired component of the incident magnetic field adds to the bias field incident on the first set of magnetoresistive sensor elements, and subtracts from the bias field incident on the second set of magnetoresistive sensor elements. The magnetic field sensor may then sense the desired component of the incident magnetic field by simply sensing the difference in resistance of the first set of magnetoresistive sensor elements and the second set of magnetoresistive sensor elements.

Abstract: A magnetoresistive memory array which has a row of active sense lines with each sense line including magnetoresistive bits and word lines extending over the bits. Each active sense line ending in a termination bit having a configuration selected to cause an adjacent bit to experience a magnetic field similar to that experienced by the remaining bits in the sense line. An inactive sense line located at each end of the row of active sense lines.

Abstract: A logic circuit includes a potential coupled to a node and a first transistor coupled between a first input and the output with its gate coupled to the node. At least a second transistor is coupled between the node and ground with its gate coupled to a second input. At least a third transistor is coupled between the output terminal and ground with its gate connected to the second input.

Abstract: A word line structure, and method of manufacture therefor, for a monolithically formed magnetoresistive memory device having a magnetic field sensitive bit region. In a preferred embodiment, the word line structure includes a dielectric layer having an etched cavity formed therein, wherein the cavity has a bottom surface and two spaced side surfaces. A magnetic field keeper is provided adjacent to the back and/or side surfaces of the cavity. A conductive word line is also provided in the cavity and adjacent to the magnetic field keeper to at least substantially fill the cavity. A polishing step may be used to remove any portion of the magnetic field keeper and/or conductive word line that lie above the top surface of the dielectric layer to provide a planer top surface.

Abstract: An integrated magnetic field sensing device has magnetic field sensing elements arranged in an electrical bridge. A first spiral coil provides a setting and resetting function. Second and third coils are arranged to carry a common current and produce magnetic fields useful for test, compensation, calibration, and feedback applications.

Abstract: A pressure transducer with a flame arrester has a header with a sensor mounted at a surface within a cavity in the header. A diaphragm in contact with the fluid media to be measured seals the cavity. A flame arrester is shaped for receipt in the cavity and is surrounded by fill fluid. The flame arrester provides a flame-extinguishing path between the flame arrester and surface within the cavity.

Abstract: A package for shielding a circuit containing magnetically sensitive materials from external magnetic fields. A shield attached to a base of the package is connected by vias to a first conductive plane. A shield attached to a lid of the package is connected by vias to a second conductive plane. The first shield and the second shield are electrically interconnected. Conductive leads extend from the package and are connected internally to the circuit.

Abstract: A pair of complementary MOSFET's having regions of a common conductivity type separating the source and drain regions thereof which are provided on a support structure formed of an electrical insulating layer on a semiconductor material base. MOSFET's has a gate oxide layer on which is provided a gate semiconductor structure, with these structures each being of a common conductivity type and located across the gate oxide layers from the corresponding common conductivity type region.

Abstract: Method for forming a CMOS transistor in a silicon layer positioned above an underlying buried oxide layer including isolating a first active area and a second active area; forming an n-well and a p-well having specified back gate threshold voltages; forming gates over the wells; forming a lightly doped drain region in the p-well that extends through the silicon layer; and implanting ions to form a source and a drain region in the p-well to provide a lightly doped drain drift region.

Abstract: A process of providing a bond pad arrangement for use with a thermocompression wire bonder including a primary bond pad for connection of an integrated circuit during a production assembly process, and a secondary test bond pad contiguous with the primary bond pad for connection of a wire to the integrated circuit. Including performing a test sequence, and removing the wire from the secondary test bond pad.

Abstract: Method for testing bare semiconductor die which includes providing a test substrate with a die receiving surface and bond pads with conductive traces which extend away from the surface and are connected to leads that may be contacted with test probes. A vacuum source is applied to an aperture in the die receiving surface. Atmospheric pressure holds the die in place during the connection of thin wires. After connection, the die is held in place during testing by the thin wires.

Abstract: A CMOS output driver circuit with p-channel substrate tracking provides an output driver to full power supply voltage. The circuit is especially useful as a redundant circuit where its power supply connection is connected to ground and the circuit is kept in unbiased storage until it is needed.

Abstract: A method for manufacturing magnetoresistive sensors whereby a first determination of an anisotropy field of the magnetoresistive material is made and an annealing temperature is selected based on a desired final value of the anisotropy field.

Abstract: A test circuit for input threshold voltage of an integrated circuit uses input pins and logic elements connected in a tree arrangement. The output of the tree controls programmable resistors to indicate pull-up or pull-down. The test circuit eliminates the need for a dedicated output pin for the testing formation.

Abstract: Thermally isolated circuit formed on a semiconductor on insulator structure includes a semiconductor surrounded by a semiconductor outer portion with an insulator therebetween. A cavity formed in the underlying semiconductor substrate opposite to the island provides thermal isolation.