Abstract: Optically powered sensing apparatus which has a photodiode for converting optical power to electrical energy and a switching voltage converter for optimizing power transfer from the photo diode. A controller intermittently provides a synchronizing pulse train and a synchronizing receiver detects periods when optical power drops to zero. A transducer with driving and readout electronics provides electrical parameter signals which are digitized and synchronously transmitted to the controller during the periods of no optical power from the controller. Voltage regulation, impedance matching, and temperature compensation of the photodiode optimize power transfer.
Abstract: A method for fabricating polysilicon resistors of intermediate high value for use as cross-coupling or =ingle event upset (SEU) resistors in memory cells. A thin polysilicon film is implanted with arsenic ions to produce a predetermined resistivity. The thin film is then implanted with fluorine ions to stabilize the grain boundaries and thereby the barrier height. Reducing the variation in barrier height from run to run of wafers allows the fabrication of reproducible SEU resistors.
Type:
Grant
Filed:
December 13, 1991
Date of Patent:
May 18, 1993
Assignee:
Honeywell Inc.
Inventors:
Michael S. Liu, Gordon A. Shaw, Jerry Yue
Abstract: Disclosed is a composition and method for providing conductive electronic component high strength bonding. The composition comprises an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead. The method invention comprises providing a leadframe comprising at lest one of power, ground, and signal conductive elements; and preforming solder material onto one of the conductive elements, the solder bonding material having an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead.
Type:
Grant
Filed:
July 11, 1991
Date of Patent:
November 10, 1992
Assignee:
Honeywell Inc.
Inventors:
Thomas J. Dunaway, Richard K. Spielberger, Lori A. Dicks, Jerald M. Loy
Abstract: A single bimetal automatic changeover thermostat has heating, cooling and changeover switches mounted to the bimetal. A single control point adjustment lever for rotating the bimetal has separate shaped heat and cool set point indicators which are movable along a temperature scale.
Abstract: A method of forming a self-aligned contact to a transistor component located on a semiconductor substrate comprising forming a transistor component opening in a masking layer overlying a semiconductor substrate and using epitaxial lateral overgrowth to form a self-aligned contact, the epitaxial overgrowth beginning in the masking layer opening at an upper surface of the semiconductor substrate and extending normal to and laterally over the masking layer surface.
Abstract: A scratch reducing shadow mask for providing vapor deposition patterns of bonding metals onto a surface of a die. The shadow mask comprises a top surface and a bottom surface which define a plurality of vias for permitting vaporized bonding metals to pass through the mask. Mask bottom surface comprises a plurality of recessed regions to minimize the contact area of the mask with the die during the vapor deposition process.
Type:
Grant
Filed:
October 31, 1990
Date of Patent:
August 18, 1992
Assignee:
Honeywell Inc.
Inventors:
Thomas J. Dunaway, Richard K. Spielberger
Abstract: A decoupling apparatus for a microcircuit provides for a custom capacitor to be placed directly on the passivated upper surface of the integrated circuit or alternatively to be placed directly under the integrated circuit.In another alternative, multiple standard chip capacitors are placed directly on the passivated upper surface and connected by wire bonds to metal bars also resting on the upper surface.
Type:
Grant
Filed:
January 2, 1991
Date of Patent:
August 18, 1992
Assignee:
Honeywell, Inc.
Inventors:
Michael W. Heinks, Thomas J. Dunaway, Richard Spielberger
Abstract: A flexible chip interconnection includes a flexible film having interconnection lines formed on opposite sides thereof, with selected of the interconnection lines from one side connected by through-film conductors to interconnection lines on the other side. Insulating layers cover both sets of interconnection lines. Multi-chip circuits can be formed on the film with the interconnection lines directly connecting the chips.
Abstract: Disclosed is a stacked leadframe assembly for use with integrated circuit chips. The assembly comprises multiple leadframes arranged in stacked relation. Each leadframe comprises conductive elements and solder bumps for electrically and mechanically connecting selected conductive elements of the leadframes.
Type:
Grant
Filed:
March 26, 1991
Date of Patent:
March 24, 1992
Assignee:
Honeywell Inc.
Inventors:
Thomas J. Dunaway, Richard K. Spielberger, Jerald M. Loy, Lori A. Dicks, Francis J. Belcourt
Abstract: A method and apparatus for accurately positioning a semiconductor chip onto a die bond pad region of a semiconductor package. A frame is constructed for slidable contact with peripheral walls of a semiconductor package die cavity. A frame central aperture with a wide upper opening and a narrower lower opening guides a semiconductor chip dropped therethrough into a precise position in the die cavity.
Type:
Grant
Filed:
October 31, 1990
Date of Patent:
December 24, 1991
Assignee:
Honeywell Inc.
Inventors:
Thomas J. Dunaway, Richard K. Spielberger, Lori A. Dicks
Abstract: An optical interconnect for coupling a collimated free space light beam to a raised channel waveguide formed on a substrate. A modified graded index rod lens has a flattened polished surface parallel to its optical axis. The rod lens is positioned with the flattened surface adjacent the substrate and an endface spaced from the waveguide endface so that a collimated light beam entering the lens will be focused onto the waveguide endface.
Abstract: Disclosed is a composition and method for providing conductive electronic component high strength bonding. The composition comprises an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead. The method invention comprises providing a leadframe comprising at least one of power, ground, and signal conductive elements; and preforming solder material onto one of the conductive elements, the solder bonding material having an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead.
Type:
Grant
Filed:
September 28, 1990
Date of Patent:
November 19, 1991
Assignee:
Honeywell Inc.
Inventors:
Thomas J. Dunaway, Richard K. Spielberger, Lori A. Dicks, Jerald M. Loy
Abstract: Disclosed is a semiconductor chip package comprising a plurality of programmable pads located on a surface of the package, each pad being adapted for interconnection with a semiconductor chip. The package also includes a plurality of signal connectors located on a surface of the package. In addition the package includes a plurality of signal connections, each signal connection providing an electrically conductive path between an individual programmable pad and a corresponding individual signal connector. A plurality of dedicated power or ground connectors are also located on a surface of the package. Conductive paths within the package provide apparatus for selectively connecting any programmable pad to a power or ground connector, any pad so connected also remaining connected to a corresponding signal connector.
Type:
Grant
Filed:
October 13, 1989
Date of Patent:
November 19, 1991
Assignee:
Honeywell Inc.
Inventors:
Richard K. Spielberger, Thomas J. Dunaway
Abstract: Disclosed is a radial solution to integrated circuit chip carrier pitch deviation. The invention comprises a chip carrier comprising a carrier body with a plurality of fine pitch metalizations. Each of the metalizations includes an axis with an extension line that intersects a point common to all axes so that each metalization may be functionally utilized independent of carrier body shrinkage tolerances.
Abstract: A method of forming a self-aligned contact to a transistor component located on a semiconductor substrate comprising forming a transistor component opening in a masking layer overlying a semiconductor substrate and using epitaxial lateral overgrowth to form a self-aligned contact, the epitaxial overgrowth beginning in the masking layer opening at an upper surface of the semiconductor substrate and extending normal to and laterally over the masking layer surface.
Abstract: A method for storing selected magnetic states in magnetic bit structures so as to assure establishment of the desired state therein. A first word line current, used for storing a magnetic state, is followed by providing a second word line current. The second line current assures establishment of the desired state in the magnetic bit structure by overcoming any pinning of a magnetic wall.
Type:
Grant
Filed:
April 4, 1990
Date of Patent:
October 22, 1991
Assignee:
Honeywell Inc.
Inventors:
James M. Daughton, Allan T. Hurst, Jr., Arthur V. Pohm
Abstract: A proximity switch for use with a single optical source of energy. A passive fiber-optic magnetometer includes a Michelson type magnetometer in which one of the legs is sensitized to magnetic fields. A fiber-optic data link connects the magnetometer to the single optical source of energy and to a photo detector. A permanent magnet positioned adjacent the magnetometer causes constructive interference which is detected by the photo detector.
Abstract: A combination pilot burner and generator including a pilot burner head for deflecting a pilot flame in a given direction. The proper location of the generator for optimum flame sensing is assured by securing the generator to the pilot burner head by welding or other securement.