Patents Represented by Attorney Gregory L. Mayback
  • Patent number: 6966919
    Abstract: A surgical instrument includes an end effector having a clevis and first and second jaws mutually rotatable between open and closed positions. The jaws are proximally directed and laterally displaced relative to a longitudinal axis of a control shaft of the instrument. The jaws hold first and second parts of a fastener, respectively. The first part includes a base having upstanding tissue piercing posts, and the second part includes another base defining apertures for receiving the posts, as well as a portion movable relative to the second base. When the upstanding posts are inserted into the apertures, the movable portion can be moved into a second configuration to lock the parts of the fastener together. The instrument is adapted to move the second part into the second configuration. A method for using the apparatus and fastener are also provided.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: November 22, 2005
    Assignee: ID, LLC
    Inventors: Robert Sixto, Jr., Kevin W. Smith, Juergen A. Kortenbach, Michael Sean McBrayer, Charles R. Slater
  • Patent number: 6835603
    Abstract: A method for producing semiconductor laser components in which, a number of chip mounting areas are formed on a cooling element having an electrically insulating carrier that is in the form of a plate. A number of semiconductor laser chips are then fit to the cooling element, with one semiconductor laser chip being arranged on each chip mounting area. Finally, the cooling element, with the semiconductor bodies fit on it, is subdivided into a number of semiconductor laser components.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: December 28, 2004
    Assignee: Osram Opto Semiconductors GmbH & Co. OHG
    Inventors: Bruno Acklin, Stefan Grötsch
  • Patent number: 6835612
    Abstract: A gate layer stack formed with at least two layers is firstly patterned anisotropically and then thelower layer is etched. An isotropic, preferably selective etching step effects a lateral undercutting, i.e. removal of the lower layer as far as the predetermined channel length to form a dimensionally accurate T-gate transistor with a very short channel length.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: December 28, 2004
    Assignee: Infineon Technologies AG
    Inventors: Annalisa Cappellani, Ludwig Dittmar, Dirk Schumann
  • Patent number: 6835417
    Abstract: The ALD process chamber has heating radiation sources and the process sequence includes rapid temperature changes on a substrate surface of a substrate arranged in the ALD process chamber. The temperature changes are controlled and the ALD and CVD processes are optimized by in situ temperature steps, for example in order to produce nanolaminates.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: December 28, 2004
    Assignee: Infineon Technologies AG
    Inventors: Annette Saenger, Bernhard Sell, Harald Seidl, Thomas Hecht, Martin Gutsche
  • Patent number: 6836283
    Abstract: The method is for setting the line width of recorded image lines of a focused image beam in an exposer. The exposure point has a diameter and an area with a non-uniformly distributed power density. The recording material has a first exposure threshold and is exposed with an energy density near a second exposure threshold that is substantially higher than the first exposure threshold. The recording material can be a photopolymer printing plate. The line width of the recorded image lines is determined from the distribution of the power density over the area of the exposure point by integrating the time variation of the power density resulting from the exposure speed of the laser beam. The line width is set, by changing the diameter of the exposure point and/or by the laser power, such that the line width is substantially equal to the line spacing.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: December 28, 2004
    Assignee: Heidelberger Druckmaschinen AG
    Inventor: Jörg-Achim Fischer
  • Patent number: 6836440
    Abstract: Two methods check functional capability of electrical connections between address lines of a printed circuit board of a memory module and address line contacts of an integrated semiconductor memory chip mounted on the printed circuit board. Ruptured solder contacts are conventionally examined optically or investigated by electrical resistance measurements; however, the latter do not work in the case of memory modules with a number of semiconductor chips, the pin contacts of which are connected in parallel by the address lines. The methods make it possible to locate interrupted contacts on individual address lines by the indirect use of a write-read access to the semiconductor memory chip, specifically utilizing the misrouting of writing and reading commands produced by defective contact connections.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: December 28, 2004
    Assignee: Infineon Technologies AG
    Inventors: Frank Adler, Thomas Huber, Manfred Moser
  • Patent number: 6834949
    Abstract: A device for holding a sheetlike article on a movable underlying surface for transporting the sheetlike article in at least one direction selected from the group consisting of a direction into and a direction out of an operating station having a printing unit, includes a member having a surface underlying the sheetlike article, the sheetlike article being retainable by pneumatic pressure on the surface, a screening device disposed locally fixedly with respect to an operating station, the screening device serving for reducing an airflow in a region of the printing unit at least with respect to adjacent regions, the reduction in the airflow resulting from the sheetlike article being held on the underlying surface.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: December 28, 2004
    Assignee: Heidelberger Druckmaschinen AG
    Inventor: Martin Greive
  • Patent number: 6833298
    Abstract: The present invention relates to a method for fabricating a semiconductor component having at least one transistor cell and an edge cell. The method includes providing a semiconductor body having a channel zone in the region of a transistor cell, a first terminal zone in the region of an edge cell, an insulation layer applied to a front side of the semiconductor body, and an electrode layer applied to the insulation layer. The electrode layer and the insulation layer are patterned in the region of the edge cell and the transistor cell and serve for fabricating complementary doped regions in the channel zone and the first terminal zone. In the region of the edge cell, the patterned electrode layer serves for the subsequent removal of the complementary doped zone during the fabrication of a contact hole.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: December 21, 2004
    Assignee: Infineon Technologies AG
    Inventor: Hans Weber
  • Patent number: 6833584
    Abstract: A trench power semiconductor component is described which has an edge cell in which an edge trench is provided. The edge trench, at least on an outer side wall, has a thicker insulating layer than an insulating layer of trenches of the cell array. This simple configuration provides a high dielectric strength and is economical to produce.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: December 21, 2004
    Assignee: Infineon Technologies AG
    Inventors: Ralf Henninger, Franz Hirler, Manfred Kotek, Joost Larik, Markus Zundel
  • Patent number: 6834377
    Abstract: A layout of an integrated electrical circuit on a memory unit of a computer system includes one or more instantiations of at least one circuit network description as well as information about the instantiations. A raw data structure represents the logical configuration of the layout and associates each instantiation with one, and only one, polygon data structure. A modified data structure is produced to represent the layout, which associates a circuit network description with one, and only one, polygon data structure, wherein the geometrical differences between the instantiations of this circuit network description are taken into account by variants in the polygon data structure.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: December 21, 2004
    Assignee: Infineon Technologies AG
    Inventors: Peter Baader, Burkhard Ludwig
  • Patent number: 6834179
    Abstract: In the access control system, a code transmitter-end transceiver unit and a vehicle-end transceiver unit emit signals approximately synchronously on approximately the same carrier frequency. As a result of superimposition, a new code signal arises and its code information item is compared with an expected set point code information item. When there is correspondence, an enable signal for locking or unlocking or releasing the immobilizer is generated. The synchronous transmission/reception makes illegitimate monitoring more difficult.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: December 21, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventor: Nikolas Bergerhoff
  • Patent number: 6834108
    Abstract: The present invention relates to a method for improving acoustic noise attenuation, in which the method includes an adaptive control for partial-band echo compensation as well as global-band post-filtering for suppressing residual echo in hand-free devices. This method also uses a level balance as well as controllable frequency-selective echo compensation with partial-band processing. After the frequency-selective echo compensation, the signal is submitted to a post-filtering in another frequency-selective filter using a Wiener-equation adjustment algorithm (Wiener filtering). A single control value (increment vector) is used for controlling both the frequency-selective echo compensation and the other filter. This method can thus be implemented with a very reduced amount of calculations so that it can also be used in simple consumer-directed processors.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: December 21, 2004
    Assignee: Infineon Technologies AG
    Inventor: Gerhard Schmidt
  • Patent number: 6833302
    Abstract: A method for fabricating a memory cell, in particular, a DRAM memory cell, having a transistor and a trench capacitor that are connected to one another through a buried strap contact includes applying at least one diffusion barrier on an upper surface of a first filling material of the trench capacitor to prevent an undesirable outdiffusion of dopant from the first filling material. Thus, with the diffusion barrier intact, at most a dopant that is possibly present in a second filling material can outdiffuse into adjoining regions. However, the outdiffusion of dopant from the first filling material can be initiated in a targeted manner by breaking open the diffusion barrier by a thermal treatment. Through the possibility of restraining the diffusion of the dopant until a suitable point in the process, it is possible to avoid an excessive outdiffusion into a contact region with a transistor.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: December 21, 2004
    Assignee: Infineon Technologies AG
    Inventor: Arkalgud Sitaram
  • Patent number: 6833022
    Abstract: A method and a device for filtering polluted air, in which the air is successively subjected to the processes of extracting grease/fat and water, drying air still containing residual humidity, and adsorbing smells/odors. The filter device includes, in a direction of flow a vortex filter, layers of expanded metal, a filter for drying the air, and an odor filter, all in a filter housing. The filter for drying the air and the odor filter are, preferably, combined in a filter cassette that is disposed on the filter housing such that it can be changed/replaced.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: December 21, 2004
    Assignee: BSH Bosch und Siemens Hausgerate GmbH
    Inventors: Egon Feisthammel, Dieter Rosmann
  • Patent number: 6829821
    Abstract: A unit for automatically crimping ribbons of flexible flat cable has a guide surface on which a ribbon of flat cable travels. A number of crimping stations are arranged vertically offset plumb with the plane of the guide surface and designed to crimp a connector onto an end of a branch of the flat cable. A number of tilting ramps have a first end even with the plane of the guide surface when they are in the tilted state and a second end even with a crimping station. The ramp tilts toward the guide surface on command so that a predetermined branch of the ribbon follows the ramp it encounters in its path as it travels along and so that it is directed to one travels along and so that it is directed to one of the crimping stations where it receives a connector.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: December 14, 2004
    Inventor: Roel Hellemans
  • Patent number: 6828192
    Abstract: A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner capacitor electrode. An epitaxial layer is grown on the sidewall of the trench on the substrate. A buried strap is disposed between the conductive trench filling with the second intermediate layer and the epitaxially grown layer. A dopant outdiffusion formed from the buried strap is disposed in the epitaxially grown layer. Through the epitaxially grown layer, the dopant outdiffusion is further removed from a selection transistor disposed beside the trench, as a result of which it is possible to avoid short-channel effects in the selection transistor.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: December 7, 2004
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Gustin, Ulrike Grüning-Von Schwerin, Dietmar Temmler, Martin Schrems, Stefan Rongen, Rudolf Strasser
  • Patent number: D499602
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: December 14, 2004
    Assignee: BSH Bosch und Siemens Hausgerate GmbH
    Inventor: Rolf Feil
  • Patent number: D499606
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: December 14, 2004
    Assignee: BSH Bosch und Siemens Hausgerate GmbH
    Inventor: Rolf Feil
  • Patent number: D612154
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: March 23, 2010
    Inventor: Peter Reisenthel
  • Patent number: D627164
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: November 16, 2010
    Inventor: Peter Reisenthel