Abstract: A redundancy address in a plurality of memory devices is identified by at least two protocols available in an electric system. The first protocol is a mode register set command (or extended mode register set command). A chip select signal determines one of a plurality of memory modules, where a memory device is identified with at least one data port. Alternatively, a data strobe port or a data mask port may be preferably used for the selection of the memory devices instead of using the data port. The second protocol is a RAM access command which identifies a defective memory cell address (redundancy address) within the selected RAM by way of a plurality of address ports (ADRs). A redundancy address programming method is realized by way of electrically programmable fuses or by dynamically programmable redundancy latches integrated in each memory. The electric system configuration preferably includes a non-volatile storage device for storing a data port organization for the memory devices.

Abstract: A method for accurately extracting capacitance and inductance parasitics from an electrical network representing a three-dimensional wiring of an integrated circuit chip or module is described. The extraction process can be performed either prior to or after completing a detailed wiring of the chip. In the former case, the method utilizes congestion information and approximate wiring length data to estimate the probability of encountering a particular pattern and the most accurate estimated capacitance which can arrived at. In the latter case, the wiring is partitioned into three-dimensional recognizable patterns, and a database of precomputed parasitics for each pattern is queried in order to obtain highly accurate parasitics within a limited number of machine cycles. The number of patterns is assumed to be sufficiently small to be memory and time efficient and to be arrived at in real-time.

Abstract: A memory device that includes a plurality of data storage cells; at least one redundancy data storage cell; a redundancy match detection circuit; and a means for coupling programmable fuses to the redundancy match detection circuit, wherein a defective data storage is replaced by one redundancy data storage when the redundancy match detection detects a pre-determined condition set by said programmable fuse is described. Decoding is accomplished by a data bus selecting the e-fuse to be blown. The data bus is also used for reading the state of the e-fuses to ensure that the e-fuses are correctly blown. Power is effectively applied to the selected e-fuses while sharing the data bus for e-fuse decoding and verification. In order to reduce the number of communication channels between e-fuses and the redundancy match detection circuitry, the transfer operation uses time multiplexing, allowing e-fuse information to be transferred to the redundancy match detection circuitry sequentially.

Abstract: A defect management engine (DME) for memories integrates a plurality of redundancy data cells and a plurality of redundancy address cells in the same array. The redundancy data cells are used for replacing defective cells in the memories. The redundancy address cells store the addresses of the defective cells. The memories are preferably sub-divided into a plurality of domains. A plurality of defective cells in each domain are supported by a plurality of repair units, each consisting of one or more redundancy data bits and redundancy address bits in the DME. When one or more data bits are read from a domain in the memory, the corresponding wordline in the DME simultaneously activates a plurality of repair units coupling to the wordline (self-contained domain selection). The redundancy data bits and the redundancy address bits are also read from the redundancy data cells and redundancy address cells, respectively.

Abstract: A low programming voltage anti-fuse formed by a MOSFET (or MOS) or by a deep trench (DT) capacitor structure is described. Lowering the programming voltage is achieved by implanting a dose of heavy ions, such as indium, into the dielectric directly on the substrate or indirectly through a layer of polysilicon. The programming voltage can also be lowered on the MOSFET/MOS capacitor anti-fuse by accentuating the corners of active areas and gate areas of the device with suitable layout masks during processing. Silicon active area corner rounding steps should also be avoided in the fabrication of the anti-fuse to reduce the programming voltage. In the DT capacitor, lowering the programming voltage may be achieved by implanting the node dielectric of the DT anti-fuse with heavy ions either directly or through a conformal layer of polysilicon deposited on it or after the first amorphous silicon recess step during the fabrication of the DT capacitor.

Abstract: A cover assembly for a socket suitable to accommodate modules of varying thicknesses which can be advantageously used for final test and burn-in test is described. The assembly is characterized by having a low profile and includes a hinged lid; a floating shaft coupled to two cams pivoting on the floating shaft; a locking member positioned between the two cams for locking the hinged lid when in a closed position, the locking member pivoting about the floating shaft; a pressure plate for forcing the module into the socket; and stiffening members integral to the hinged lid located on opposing sides of the hinged lid and below the surface of the pressure plate for providing added strength to the assembly. The assembly also includes a heatsink inserted through an aperture located in the pressure plate, to directly contact the chip which is mounted on the module. The force applied to the chip is independent of the force applied to the module.

Abstract: A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.

Abstract: An improved wiring structure to minimize coupling between the wiring in one metalization layer of an integrated circuit chip and the wiring in an adjoining metalization layer is described. Wiring in one layer is rotated by an angle a.sub.1 with respect to the direction of the wiring in the adjoining layer. By successively rotating all the conductors of one wiring layer with respect to the wiring of the next layer, the capacitive and inductive coupling between conductors in the various layers is minimized, thereby improving the overall high-frequency performance of the chip.

Abstract: A method of wiring a plurality of integrated circuits within a chip or between chips in one or more packages by adding cluster points to a net that includes a plurality of nodes to be interconnected. The interconnected nodes are designed to meet system requirements, commonly expressed by a set of wiring rules, include among others, physical, electrical and noise constraints. The method includes matching interconnection net attributes to wiring rule logical definitions, wherein the wiring rules include rule nodes and rule connections. The rule nodes define constraints for the pins, vias and cluster point structures. The rule connections define wiring constraints between the node structures to establish the net topology. The process described is based on net ordering and checking. The net ordering, which defines the pin-to-pin connections based on the wiring rule, is performed prior to chip or package wiring.

Abstract: A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.

Abstract: A design rule checker for verifying that an integrated circuit design meets one or more geometrical constraints, the integrated circuit design being expressed as a graph data structure having at least a root node connected by a plurality of paths to one or more leaf nodes so that a single leaf node can represent multiple instances of a geometrical shape.

Abstract: An energy application apparatus and a method to operate at high speed that makes high usage of light. An exposure apparatus includes a laser oscillator, an optical shutter, imaging lenses, a screen, a vertical deflecting device, a horizontal deflecting device, a vertical moving device, a liquid crystal panel, and a controller. A light beam emitted from the laser oscillator passes through the optical shutter when in its open position, and is directed by the imaging lens onto the slit or pattern on the screen. After passing through the slit, the light is gradually made to converge by the imaging lens and to enter the galvanomirror. The galvanomirror deflects the beam by a predetermined angle in the vertical direction, and the deflected beam enters the galvanomirror. The galvanomirror deflects the beam by a predetermined angle in the horizontal direction. Thereafter, the beam exposes a desired location of the liquid crystal panel located on the stage to form an image thereon.

Abstract: A method of forming electrical conductors having sub-half-micron geometries and using a high yield process is described. Trenches provided with an overhang are positioned where a metal interconnection is to be formed. A composite insulator layer is deposited and is followed by laterally filling with metal the trench under the overhang. Excess metal is then chem-mech polished. Only the non-crucial neck of the metal wiring is left exposed during polishing. Since spacing between the exposed metal lines is increased, it requires longer distances for the metal to smear and cause unwanted shorts. Three methods are described to laterally fill the trenches under the overhang. A first method describes the process parameters to achieve lateral deposition by high surface mobility and low sticking coefficient. A second method teaches a technique of inducing micro-creep to laterally fill the trenches under the overhang.

Abstract: A fault-tolerant memory device provided with a variable domain redundancy replacement (VDRR) arrangement is described. The memory device includes: a plurality of primary memory arrays; a plurality of domains having at least portions of one domain common to another domain to form an overlapped domain area, and at least one of the domains overlapping portions of at least two of the primary memory arrays; redundancy units, coupled to each of the domains, for replacing faults contained within each of the domains; control circuitry for directing at least one of the faults within one of the domains to be replaced with the redundancy units, wherein at least one other fault of the one domain is replaced by the redundancy unit coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements.

Abstract: A sub-block redundancy replacement memory configuration for repairing a plurality of faulty memory arrays, each consisting of a plurality of memory cells arranged in a first matrix formation, supported by first row decoders and first sense amplifiers, by combining at least two with at most n-1 out n sub-block redundancy arrays, each consisting of a plurality of redundancy memory arrays arranged in a second matrix, and supported by second row decoders and second sense amplifiers. Since additional sub-block redundancy arrays are available, it is possible to repair a defective memory array even if one or more block faults are present in the memory. The number of cells in the redundancy arrays is less than the number of cells in the memory arrays, substantially reducing the silicon overhead. Optionally, the sub-block redundancy memory arrays are distributed within at least two units, each consisting of a plurality of memory arrays, at least one sub-block redundancy array and corresponding columns decoders.

Abstract: A heated apparatus, positioned in the X, Y, and Z directions, for forming fine lines of molten material on a substrate. The apparatus includes a pen having a refractory tip wetted with material in a molten state. The tip is attached to a V-shaped heater to form a heater assembly. The ends of the V-shaped heater are welded to the pins of a three lead TO-5 package base. The pen is then mounted on an apparatus adapted to direct writing. To that end, the pen is attached to a supporting device capable of moving in the X, Y, and Z directions. When the welding point of the tip/heater assembly reaches the melting point of the material to be deposited, it is dipped in a crucible containing the material in a molten state. The welding point nucleates a minute drop of the molten material, forming a reservoir. A thin film of material flows from the reservoir and wets the tip, which is then brought in contact with the substrate upon which the desired pattern is to be formed.

Abstract: A method and apparatus for repairing a memory device through a selective domain redundancy replacement (SDRR) arrangement, following the manufacture and test of the memory device. A redundancy array supporting the primary arrays forming the memory includes a plurality of redundancy groups, at least one of which contains two redundancy units. A redundancy replacement is hierarchically realized by a domain that includes a faulty element within the redundancy group, and by a redundancy unit that repairs the fault within the selected domain. SDRR allows a domain to customize the optimum number and size redundancy units according to existing fault distributions, while achieving a substantially saving in real estate, particularly over the conventional flexible redundancy replacement, in term of the number of fuses (10-20%). By combining several types of redundancy groups, each having a different number of redundancy elements, full flexible redundancy replacement can also be achieved.

Abstract: A method for determining if an undesirable feature on a photomask will adversely affect the performance of the semiconductor integrated circuit device that the mask is being used to create. The method includes inspecting the photomask for undesirable features and analyzing the designed features close to the defects. This analysis is performed on lithographic images that represent the image that is transferred onto the semiconductor wafer by the lithography process. This analysis takes into account the effect of variations that are present in the lithography process. Through knowledge of the effects of variations in mask critical dimension of a feature on the lithographic image of that feature, the analysis results in the assignment of an equivalent critical dimension error to the defect. This equivalent critical dimension error is then compared to the mask critical dimension error specification to determine whether or not the defect will adversely affect the device.

Abstract: A programmable/reprogrammable fuse arrangement that includes two fuse links provided each with an output port and an exclusive-or gate connected to the output port of each of the two fuses, wherein the fuse arrangement is reprogrammed by successively blowing both of the two fuse links is described. The programmable/reprogrammable fuse arrangement can be extended to a plurality of fuses and cascaded exclusive-ORs such that each fuse link provides one leg of the gate and the previous stage, the second. Thus, for N fuse links and N exclusive-ORs, the fuse arrangement thus formed can be reprogrammed a total of N times by sequentially blowing one fuse link at a time. The arrangement ceases to be reprogrammable once all the fuse links have been blown. The reprogrammable fuse arrangement is of particular importance for semiconductor memories and microprocessors, as for instance, for bringing in-line redundancy units attached to a fuse link.

Abstract: A method and apparatus for repairing a semiconductor memory device. A row redundancy replacement arrangement is provided to repair the memory device consisting of a first plurality of redundant true word lines and a second plurality of redundant complement word lines to simultaneously replace the same first number of first normal word lines and the same second number of the normal complement word lines. An address reordering scheme, preferably implemented as a word line selector circuit and controlled by redundancy control logic and address inputs, allows the redundant true (complement) word lines to replace the normal true (complement) word lines when making the repair. The redundancy replacement arrangement ensures that consistency of the bit map is maintained at all times, irrespective whether the memory device operates in a normal or in a redundancy mode. This approach introduces an added flexibility of incorporating the redundancy replacement without affecting the column access speed.