Abstract: An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.

Abstract: A process for removing a resist material containing a chlorine residue from an organic substrate. The process first removes the chlorine residue from the resist material by exposing the resist material to an abbreviated plasma which also removes a portion of the resist material. The remainder of the resist material is removed by exposing the resist material to a solvent which does not affect the organic substrate.

Abstract: A method of achieving automatic learning of an input vector presented to an artificial neural network (ANN) formed by a plurality of neurons, using the K nearest neighbor (KNN) mode. Upon providing an input vector to be learned to the ANN, a Write component operation is performed to store the input vector components in the first available free neuron of the ANN. Then, a Write category operation is performed by assigning a category defined by the user to the input vector. Next, a test is performed to determine whether this category matches the categories of the nearest prototypes, i.e. which are located at the minimum distance. If it matches, this first free neuron is not engaged. Otherwise, it is engaged by assigning the matching category to it. As a result, the input vector becomes the new prototype with the matching category associated thereto. Further described is a circuit which automatically retains the first free neuron of the ANN for learning.

Abstract: Retrograde openings in thin films and the process for forming the same. The openings may include conductive materials formed within the openings to serve as a wiring pattern which includes wires having tapered cross sections. The process involves a two-step etching procedure for forming a retrograde opening within a film having a gradient of a characteristic that influences the etch rate for a chosen etchant species. An opening is first formed within the film by an anisotropic etch process. The opening is then converted to an opening including retrograde features by an isotropic etch process which is selective to the characteristic. Thereafter, the retrograde opening is filled with a conductive material, in one case, by electroplating or other deposition techniques.

Abstract: An assembly consisting of three dimensional stacked SOI chips, and a method of forming such integrated circuit assembly, each of the SOI chips including a handler making mechanical contact to a first metallization pattern making electrical contact to a semiconductor device. The metalized pattern, in turn, contacts a second metallization pattern positioned on an opposite surface of the semiconductor device.

Abstract: An apparatus for receiving an input clock signal to an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the apparatus includes a CMOS receiver configured to receive the input clock signal and a PECL receiver configured to receive the input clock signal. The PECL receiver shares a common output node with the CMOS receiver. A receiver selection mechanism is coupled to the CMOS receiver and the PECL receiver, with the receiver selection mechanism alternatively activating or deactivating the CMOS receiver and the PECL receiver.

Abstract: A method of using diamond or a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate using a damascene process flow. The diamond or diamond-like carbon layer is deposited onto the surface of the substrate before patterning the metal level. A protective layer is then deposited over the diamond or diamond-like carbon polish-stop layer, wherein such protective layer may act as an additional polish-stop layer. Together, the diamond or diamond-like carbon polish-stop layer and the protective layer are used as a hard-mask for patterning the trenches that will become the metal features, wherein such protective layer protects the diamond or diamond-like carbon polish-stop layer during the patterning process. After deposition of a conductive metal layer, the dielectric substrate is polished to remove excess conductive material, as well as topography.

Abstract: A process for the electrolytic deposition of a metal, preferably copper or an alloy of copper, directly onto a barrier layer coated on a dielectric layer. The process is advantageous because it electrolytically deposits metal in a pattern that is either the duplicate of a first conductive pattern under the dielectric or the inverse image of the first conductive pattern, depending on the first conductive pattern shape. Thus, metal is deposited on the barrier layer duplicating a first conductive pattern under the dielectric layer when the first pattern is a serpentine pattern and the metal deposits in the spaces between the conductive lines of a first conductive pattern of a discrete passive element such as a spiral.

Abstract: A CMOS SRAM cell provided with PFET devices as passgate transistors is described to reduce the surface area taken by the pull-up and pull-down devices. A six-transistor, single-port SRAM cell is shown to dissipate 75% less power when compared to conventional cells, and its cell stability improved by a factor of 2. The power saving is the result of the differential sensing made possible with the PFET passgate devices, the smaller standby off-current of the smaller devices and the smaller loading of the short bit lines. The overall SRAM cell is significantly smaller than conventional cells in view that all the six transistors take minimum dimensions. The cell stability is also improved by having the current leakage margin increased to 40&mgr; from a conventional cell current of 10 &mgr;a. In another aspect of the invention, an eight-transistor, dual-port cell, the more balanced proportion of 4 PFETs and 4 NFETs in the cell allows a surface area saving of 50% over a conventional layout of 2 PFETs and 6 NFETs.

Abstract: A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.

Abstract: A circuit architecture and methodology for providing burst data transfer in high-speed digital circuit applications implements a sequence of overlapped global-pointer signals for generating corresponding sequence of non-overlapped local-pointer signals. One of the global pointer signals starts to be activated per cycle and the pulse width of each global pointer signal is greater than the burst cycle time. A global pointer signal <i> of a sequence (where i is one of the integers <1:n>) is used to generate a corresponding local pointer signal <i> that is reset by detecting a time at which the global pointer signal <i+1> starts to be activated. This allows for generation of reliable non-overlapped local pointer signals, while using overlapped global pointer signals. Each local generated pointer signal is used to accomplish a respective data transfer, e.g., from an individual latch to a single data line.

Abstract: A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.

Abstract: A thin flexible multi-layered printed circuit cable manufactured by a relatively simple process and having improved electro-magnetic interference and impedance characteristics is described. The cable includes: an insulating substrate layer; a wiring layer formed on the insulated substrate layer; a coating layer laminated on the wiring layer; a first non-woven metal fiber layer laminated on the coating layer; and a second non-woven metal fiber layer laminated on an opposite surface of the substrate layer. Because the cable is coated with a conductive non-woven or woven metal fabric, electromagnetic waves generated during transmission of high speed data are fully shielded. The non-woven or woven fabric having a wide surface area, is soft and can make good surface-to-surface contact.

Abstract: A one step method for curing encapsulant and joining Ball Grid Array (BGA) solder balls comprises curing an encapsulant material simultaneously with the joining of the eutectic material of the apparatus whether that eutectic material is a solder paste or preform, the balls being of a higher melt material or the balls themselves being an eutectic material. The method performs both functions in one pass through a furnace avoiding the separate and time consuming encapsulant and/or underfill curing step.

Abstract: A process for forming a small grain structure in a material within a semiconductor device near the interface of an adjacent dissimilar material, to result in a highly diffusive grain structure. The highly diffusive grain structure formed within one material enhances diffusion of a dopant impurity, and provides for improved dopant control in an adjacent dissimilar material.

Abstract: A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate.

Abstract: A Defect Leakage Screen Test apparatus and method is introduced to eliminate or reduce steps in the failure analysis process of memory devices, such as DRAM cells, or to eliminate the necessity for the application of a physical failure analysis on the memory device. Special single bit failures due to leakage current, junction current, or threshold leakage current, are characterized by varying the p-well voltage of the memory device during the read operation of the test. The p-well voltage is varied with a test code Initial Program Load (IPL). Additional logic is provided on the memory IC to decode the IPL logic signals. In order to perform the p-well varying test, the memory device is provided with the following: IPL decoding logic; a reference voltage generator; an IPL voltage reference multiplexor; a p-well voltage feed-back circuit; and a differential amplifier circuit.

Abstract: A method for detecting phase features or phase defects on photomasks for optical lithography is described. The asymmetric imaging behavior through focus of defects or features with a phase other than 0° or 180° is used to distinguish them from other features on the mask. The mask is inspected at equally spaced positions about an optimum focus in both positive and negative directions. The images are subtracted from one another to produce a differential image of the mask. While opaque features as well as transmitting features at 0° and 180° behave identically at positive and negative defocus, thus leading to a zero-valued differential image, the focus asymmetry of phase defects and features produces a non-zero differential image from which these phase defects and features can be located.

Abstract: A method and apparatus for providing a self-adjusting burn-in test to a device-under-test by dynamically regulating critical burn-in test parameters, such as the supply voltage, and modifying the test conditions, avoiding in the process over and under burn-in. More specifically, the method includes setting an initial set of burn-in operating test conditions and repeatedly adjusting the burn-in operating test conditions while performing the burn-in test until a predetermined reliability target is achieved. The apparatus being described includes a test target, a tester, a reliability analyzer, and a burn-in controller. With this system, the number of fails are measured during burn-in, and the final number of fails after completion of the burn-in test is extrapolated. If the number of fails exceeds a stated reliability objective, the burn-in conditions specified by burn-in controller are reduced, thereby avoiding over burn-in or in the alternative under-burn.

Abstract: A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow trench isolation device within a semiconductor substrate. The shallow trench isolation structure is divot-free and includes un-annealed dielectric material as the trench fill material. The intersection of the structure and the semiconductor surface in which it is formed, is free of silicon nitride, but the isolation structure may include a silicon nitride liner which is within the trench and recessed below the semiconductor surface.