Abstract: A DRAM cell storage capacitor is formed above the bottom of a deep trench (DT) below an FET transistor. The DT has upper, central and lower portions with sidewalls. A capacitor plate electrode, surrounding the lower DT portion that is doped with a first dopant type, is separated by an interface from a well region surrounding the upper and central portions of the DT that are doped with an opposite dopant type. A source/drain region formed at the top of the cell is doped with the first dopant type. A node dielectric layer that covers the sidewalls and bottom of the lower and central portions of the DT is filled with a node electrode of the capacitor, doped with the first dopant type, fills the space inside the node dielectric layer in the lower part of the DT. Above a recessed node dielectric layer a strap region space is filled with a buried-strap conductor. An oxide (TTO) layer is formed over the node electrode and the buried-strap in the DT.

Abstract: A fuse structure in an integrated circuit chip is described that includes an insulated semiconductor substrate; a fuse bank integral to the insulated semiconductor substrate consisting of a plurality of parallel co-planar fuse links; and voids interspersed between each pair of the fuse links, the voids extending beyond a plane defined by the co-planar fuse links. The voids surrounding the spot to be hit by a laser beam during fuse blow operation act as a crack stop to prevent damage to adjacent circuit elements or other fuse links present. By suitably shaping and positioning the voids, a tighter pitch between fuses may be obtained.

Abstract: A computer operated process (30) for inspecting patterns (32, 34) on an object (31) includes establishing different mismatch margins for different patterns (32, 34). A strict margin is associated with the pattern (32) in a critical area (12), and a relaxed margin is associated with the pattern (34) in a non-critical area (14). The inspection process (30) rejects the object (31) as being defective if a mismatch between a pattern (32, 34) and its respective master pattern (42, 44) exceeds a corresponding mismatch margin. Therefore, the inspection process (30) maintains a high standard for the pattern (32) in the critical area (12) and eases the standard for the pattern (34) in the non-critical area (14).

Abstract: A method of determining the effect of the degradation of MOSFET on the frequency of a Ring Oscillator (RO) consisting of an odd prime number of inverter stages, each of the inverters stages having an NMOS and a PMOS field-effect transistor is described.

Abstract: A single pattern-matching algorithm which allows both exact and inexact pattern-matching so that transistor-level design automation tools can reliably perform timing analysis, electrical rules checking, noise analysis, test pattern generation, formal design verification, and the like prior to manufacturing custom logic. The user (circuit designer) specifies which of each of the pattern external nets may be matched inexactly (attached to Vdd, attached to GND, and shorted to other external nets), with the remainder of the pattern external net connections being matched using exact isomorphism constraints. The method described herein achieves a substantial reduction in the number of patterns which circuit designers must generate, and altogether eliminates the need for an exponential number of patterns by providing an inexact pattern matcher to circuit designers.

Abstract: To obtain data pertaining to the surface characteristics of a sample, a control method adjusts a tilted rastered E-beam to in SEM to a first/next tilt condition and navigates the SEM-beam to a sample site. The system performs a fine alignment step. Then the system scans a region of a sample to acquire a waveform. The system analyzes the waveform to determine the DESL value for each edge of interest. The system tests whether there is sufficient information available for each structural edge. If NO, the system repeats the above steps starting by changing the value of the tilt angle to acquire another waveform. If YES, the system determines the height and sidewall angles for each structural edge. Then the system reports the sidewall angle and the structure height for each edge of the structure under test. The system then corrects the critical dimension measurement determined from 0 degrees tilt scanning.

Abstract: A voltage controlled oscillator of a phase locked loop circuit having digitally controlled gain compensation. The digital control circuitry provides binary logic input to the voltage controlled oscillator for a digitally controlled variable resistance circuit, a digitally controlled variable current transconductor circuit, or differential transistor pairs having mirrored circuitry for adjusting the V-I gain.

Abstract: A CMOS charge pump circuit with diode connected MOSFET transistors is formed with asymmetric transistors which preferably have halo source region implants with a forward threshold voltage (VthF) and with a reverse threshold voltage (VthR), with the forward threshold voltage VthF being substantially larger than the reverse threshold voltage VthR. Preferably, the halo source regions are super halos. An SRAM circuit with pass transistors and pull down transistors includes pass transistors which comprise super halo asymmetric devices.

Abstract: A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent. The oxidant preferably includes a carbon-containing oxidant component and an oxidant-noble gas component. The fluorocarbon gas is selected from CF4, C2F6, and C3F8; the hydrogen source is selected from CHF3, CH2F2, CH3F, and H2; the oxidant is selected from CO, CO2, and O2; and the noble gas diluent is selected from He, Ar, and Ne. The constituents are added in amounts to achieve an etchant gas having a high nitride selectivity to silicon oxide and photoresist. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas.

Abstract: A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the reticle mask by removing a set(s) of the features that are juxtaposed. Form unexposed resist on the workpiece. Load the workpiece and the reticle mask into the stepper. Expose the workpiece through the reticle mask. Reposition the workpiece by a nanostep. Then expose the workpiece through the reticle mask after the repositioning. Test whether the plural exposure process is finished. If the result of the test is NO the process loops back to repeat some of the above steps. Otherwise the process has been completed. An overlay mark is produced by plural exposures of a single mark. A dead zone is provided surrounding an array region in which printing occurs subsequent to exposure in an original exposure. Stepper-framing-blades are moved over the dead zone to prevent additional exposures after an initial exposure.

Abstract: A capacitor is formed in a trench in a well/substrate doped with a first polarity. A dielectric isolation collar formed on trench sidewalls is recessed below the trench top and is spaced from the trench bottom. Therebelow, a counterdoped plate electrode region surrounds the trench and a node dielectric covers the exposed sidewalls. A counterdoped conductive buffer layer or region covers the node dielectric. A conductive, lower diffusion barrier covers the buffer. A first polarity doped node conductor, which is formed over the lower diffusion barrier, is covered by a conductive, upper diffusion barrier. A counterdoped cap covers the upper diffusion barrier. A counterdoped strap region formed by outdiffusion into the substrate is juxtaposed with the edge of the cap.

Abstract: A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion.

Abstract: The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.

Abstract: An improved fin device used as the body of a field effect transistor (“FET”) and an improved process of making the fin device. The fin device allows for the fabrication of very small dimensioned metal-oxide semiconductor (“MOS”) FETs in the size range of micrometers to nanometers, while avoiding the typical short channel effects often associated with MOSFETs of these dimensions. Accordingly, higher density MOSFETs may be fabricated such that more devices may be placed on a single semiconductor wafer. The process of making the fin device results in an improved fully planarized device.

Abstract: A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon substrate. Deep trenches are etched through the upper surface SOI layer, the BOX layer and into the substrate. Each trench capacitor is formed in the substrate and, the access transistor is formed on a sidewall of the SOI layer. Recesses are formed in the BOX layer at the SOI layer. A polysilicon strap recessed in the BOX layer connects each polysilicon storage capacitor plate to a self-aligned contact at the source of the access transistor. Dopant is implanted into the wafer to define device regions. Access transistor gates are formed along the SOI layer sidewalls. Shallow trenches are formed and filled with insulating material to isolate cells from adjacent cells.

Abstract: An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer.

Abstract: A probe assembly consisting of a servo mechanism or actuator providing multi-direction motion; a probe mounting attached to the actuator; and pin probes attached to the probe mounting making an electrical connection to pins of a device or package under test. The pin probe includes a shaft terminating in an end section having a conical shaped recessed area. The conical feature contained in the probe allows the probe to contact a pin or array of pins that are less then ideally located, but within their geometrical tolerance. The probe assembly thus constructed, provides reliable test measurements. It also increases test throughout by minimizing test setup time when the DUT has misaligned or bent pins. The setup can be used on a manual probe station, or in a mass production bed of nails type tester. The assembly can also be in the form of a gang probe wherein pin probes are arranged in a bed of nails arrangement to make contact with all the pins of the DUT simultaneously.

Abstract: Hiding a refresh operation in a DRAM or eDRAM is achieved by tailoring an external random access time tRCext to slightly extend into the internal random access cycle time. This allows for an additional internal random access cycle time tRCint after a plurality of external random access cycles n(tRCext) when enabling the corresponding internal random access operation n(tRCint). The additional core random access cycle time tRCint is achieved at every nth clock, where n>tRCint/(tRCext−tRCint), or at a time defined by the product of tRCext and tRCint/(tRCext−tRCint). The additional core cycle time tRCint is used for refreshing the DRAM By scheduling a refresh-to-refresh period equal to or greater than the phase recovery time, a fully command compatible static random access time can be realized with DRAM cells.

Abstract: Process for forming highly conformal titanium nitride on a silicon substrate. A gaseous reaction mixture of titanium tetrachloride and ammonia is passed over the semiconductor substrate surface maintained at a temperature of about 350° C. to about 800° C. The ratio of titanium tetrachloride to ammonia is about 5:1 to 20:1. The high degree of conformality achieved by the process of the invention allows TiN layers to be deposited on structures with high aspect ratios and on complicated, three-dimensional structures without forming a large seam or void.

Abstract: A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate.