Abstract: A television vertical timebase circuit includes an arrangement (10, 25, 30, 35, 40, 45) for generating a vertical ramp voltage of first and second slopes corresponding to 4:3 and 16:9 aspect ratios. An arrangement (50,55,65) adds a predetermined voltage to a predetermined portion of the 16:9 ratio ramp voltage such that unwanted visible signals are positioned outside the visible screen area when displaying 16:9 aspect ratio pictures.

Abstract: A driver circuit (8) is arranged to switch a transistor (10) of a switched capacitor circuit, or transistors (62 and 64) of a differential switched capacitor circuit, between a first state, in which the transistor switch is closed whereby an input signal (VINP) is transferred to an output, and a second state, in which the transistor switch is open. The driver circuit includes a maximum and a minimum selection (12, 14) between the input signal and a reference voltage (VAG) , a voltage shift element (26), and switches (16, 18, 20, 22, 24), coupled to receive the input signal (VINP) and to the gate electrode of the transistor switch (10), which ensures that the gate-to-source voltage of the transistor switch (10), in the first and second states, is independent of the input signal (VINP).

Abstract: A current switching circuit (10) receives an input signal having one of an upper and a lower signal level. First (60) and second (70) transistors switch an output (115) between the upper and the lower signal level in response to the input signal. A first high resistance path (80) is selectively coupled via a gate (75) between the first transistor (60) and a first potential. A second high resistance path (90) is selectively coupled via a gate (85) between the second transistor (70) and a second potential. A control input (20) causes a logic arrangement (22) to control the gates (75, 85) thereby selectively coupling the high resistance paths (80, 90) to the first (60) and second (70) transistors such that they can switch the output at a first and a second switching speed.

Abstract: A peak voltage and peak slope detector circuit (41) of high resolution is disclosed for sensing a battery voltage during a battery charging sequence. Battery charging circuitry is disabled when a battery voltage is being sampled to eliminate error due to noise. The battery voltage is sampled at predetermined intervals for a predetermined time period which is determined by a sample timer (46). A Voltage To Frequency Converter (42) converts the battery voltage to a signal. The signal frequency corresponds to the magnitude of the battery voltage. The number of pulses output by the VFC (42) are counted during the predetermined time period. The number of pulses are counted and compared against a previous sample by a counter comparator (44) to determine peak voltage. The peak voltage occurs when the sampled count is less than the previous sample count. The rate of change of the battery voltage is monitored by a second counter comparator (47) for determining peak slope during the battery charging sequence.

Abstract: A method of forming contact pads (140) that allows for wafer level testing and burn-in of semiconductor die (22). A plurality of semiconductor die (22) are formed upon a semiconductor wafer (20), each semiconductor die (22) having a plurality of bonding pads (78). A contact pad (140) is formed overlying each bonding pad (78) and is electrically coupled to the bonding pad (78) and to wafer test pads (38) through vertical and/or horizontal wafer conductors (42-47 and 52-53 respectively) so that each semiconductor die (22) is uniquely identified. Contact pads (140) protect underlying bonding pads (78) during the formation and removal of vertical and/or horizontal wafer conductors (42-47 and 52-53 respectively). Thus, wafer level electrical testing and/or burn-in can be performed prior to designating a final packaging method for the semiconductor die (22).

Abstract: A method for generically describing measured results which includes defining a class of entities to be measured, and a set of criteria which distinguish entities within the class of entities to be measured. A computer display format is dynamically configured based on the set of criteria. The set of criteria is displayed on the computer display according to the computer display format. The values related to an individual entity are interactively specified. The set of measurements related to class of entities to be measured is displayed on the computer display screen and are associated with the set of criteria.

Abstract: A voltage controlled oscillator that completely eliminates the need for any externally mounted coil and capacitor includes a first loop and a second loop. The first loop provides band-limiting of an output signal of an amplifier through a bandpass filter to provide oscillation at a frequency of a resonant point of the bandpass filter, and the second loop controls the oscillation amplitude, so that a lowpass filter output with a 90.degree. phase is extracted from the first loop, while a bandpass filter output with a 0.degree. phase is extracted from the second loop. The voltage controlled oscillator may be used in an automatic fine tuning circuit for television.

Abstract: A history buffer system (12) for allowing the recovery of executed instructions comprises main history buffer (14) for storing addresses of issued instructions and at least one subsidiary history buffer (16, 22) associated with a predetermined type of data, such as fixed or floating point data. The subsidiary history buffer (16, 22) has a plurality of entries (Y, Z), each entry for storing a pointer to a register (18, 26) and the data stored in the register. The main history buffer (14) is arranged to store control data (fxtag, fptag) which associates the entries in a subsidiary history buffer with the appropriate issued instructions of the same data type stored in the main history buffer. The main history buffer (14) may comprise a storage entry for each issued instruction, each storage entry having a field for storing the address of an issued instruction, and at least one tag field (fxtag, fptag) corresponding to the at least one subsidiary history buffer (16, 22) for storing the control data.

Abstract: A vertical contour correcting circuit that provides contour correction of a luminance signal at a horizontal color transition area of an image, thereby minimizing dot interference at the color transition area of a reproduced image. The vertical contour correcting circuit includes a vertical band-pass filter which outputs a level difference signal. The level difference signal is delayed to produce a first delay signal. The first delay signal is delayed to produce a second delay signal. An intermediate value signal is determined from the level difference signal, the first delay signal, and the second delay signal. The intermediate value signal and the first delay signal are added together so that their carrier color signal band components are canceled out.

Abstract: An overcurrent is detected with small power consumption and at a high level of accuracy. A first transistor section 3 comprised of one NPN transistor 31 and a second transistor section 4 comprised of four NPN transistors 41-44 having the same characteristics as those of the transistor 31 are connected across a current sense resistor 2, with their emitters connected to the resistor 2. The transistors 31 and 41-44 have their bases commonly connected, with a voltage applied between their base and emitter by a voltage application unit 5, and have their collectors connected to transistors 61 and 62 which form a current mirror circuit. Once a bandgap voltage, .DELTA.V.sub.BE, i.e., a voltage difference between the base-emitter voltages of the transistor sections 3 and 4, is determined, the current density ratio of both the transistor sections 3 and 4 is determined, which is used to detect an overcurrent.

Abstract: A method for gettering metallic impurities from a semiconductor substrate (25). A gettering structure is fabricated in inactive areas of a semiconductor chip (31). The gettering structure is manufactured by forming an oxide (30) having a bird's head structure contacting a heavily doped region (28). The combination creates precipitation nuclei to which the metallic impurities migrate. The metallic impurities are sequestered by the precipitation nuclei or trap sites and rendered incapable of degrading the electrical characteristics of a semiconductor device.

Abstract: A method of determining a chrominance element for pixel signals of an optical image for a 1H delay circuit. The pixel signal(s) are first filtered through a band-pass filter to remove low frequency luminance components and a part of the filtered signal is fed through a 1H scan line delay. The result is a OH pixel signal and a 1H pixel signal one scan line apart. The OH pixel signal is added to the 1H pixel signal to generate a combed chrominance component, and the OH pixel signal and the combed chrominance component are compared to see which is the greater. If the value of the OH pixel signal is greater or equal to the combed chrominance component, the combed chrominance component is output as the chrominance element. If the value of the OH pixel signal is less than the combed chrominance component, the OH pixel signal is output as the chrominance element.

Abstract: A circuit that separates a luminance signal and a color signal so that dot interference in a color transition area of a reproduced image is minimized. A color video signal is transmitted to an adaptive bandpass filter via a vertical carrier color signal extraction filter. An output signal from the adaptive bandpass filter represents the color signal portion of the color video signal. The color signal is subtracted from the color video signal via a subtractor circuit to produce the luminance signal portion of the color video signal. Since the output signal of the bandpass filter is subtracted from the color video signal, the luminance signal portion of the color video signal is separated without being affected by different colors before and after a color transition point.

Abstract: An automotive sensor arrangement including an automotive sensor coupled via first and second wires to signal sensor evaluation means, a signal conditioning circuit comprising a first gate means connected to provide a bias operating voltage signal on said first wire to the sensor, a second gate means of similar construction to the first gate means and mounted in the same environment and first gate means, the second gate means being coupled to the second wire of the leas means for receive the voltage signal bears a predetermined relationship to the switching point voltage of the second gate means.

Abstract: An active low-pass filter suitable as a 90.degree. phase shifter circuit is provided which requires few external components when formed as an IC. The current resulting from the input signal outputted from a first impedance element is amplified by a first current amplifier, and the resulting output current is converted by a first converting means to a voltage, which is supplied via a second impedance element to a second current amplifier; the output current of the second current amplifier is converted by a second converting means to a voltage, which is outputted as a filter output, while the current corresponding to the output voltage of the second converting means is negatively fed back into the inputs of the first and second current amplifiers; furthermore, at least the current amplification factor of the first current amplifier is made controllable, thereby permitting the cut-off frequency to be varied arbitrarily.

Abstract: An operational amplifier (2) comprises a first differential stage (3) for receiving first (IP) and second (IM) input signals and for providing first (OP) and second (OM) output signals at first and second output nodes, and second (4) and third (6) differential stages, which are each coupled to receive the first (IP) and second (IM) input signals and to the first and second output nodes to provide first and second additional signals thereto. Each stage comprises two transistors (22, 24 and 32, 34) differentially connected.

Abstract: A method and an electrically conductive interconnect structure (30) for controlling electromigration. The electrically conductive interconnect structure (30) comprises a groove (33) adjacent an electrically conductive interconnect (39). The electrically conductive interconnect (39) is patterned from a deposited layer of conductive material which contains global grain microstructures. Moreover, the electrically conductive interconnect (39) is patterned to have polycrystalline and single-grain segment lengths that are less than a length at which an electromigration flux fails to overcome a gradient-driven counter flux in a line segment. The groove (33) controls the polycrystalline and single-grain segment lengths to be less than the critical length, thereby reducing electromigration.

Abstract: A method for adapting a decision directed adaptive neural network (10). The method finds the best matches between a plurality of input data vectors (16) and an associated plurality of input portion of weight vectors. The input portion of the weight vectors are adapted. The identification codes (12) which represent the sequence of best matched weight vectors are stored in a memory (12) and the associated output portion of weight vectors (22) are output. A sequence of output portion of weight vectors (22) is matched with predetermined models (21). A sequence of labels (24) associated with the best matched model is stored which identifies the categories of match data. The labels (24) are sequentially combined with the identification codes (12) to build adaptation vectors. The adaptation vectors are then used to sequentially adapt the output portion of weight vectors (22).

Abstract: In a reset signal generation circuit for generating a reset signal to a CPU in accordance with an external clock signal, illegal operation or loss of write data during a write period is prevented.A means (14) is provided for prohibiting the generation, in accordance with an external reset signal (RST), of a reset signal (RESET) to the CPU during a data write period of the CPU, and, according to a preferred embodiment of the invention, a means is provided for holding the external reset signal until a reset signal is generated to the CPU.

Abstract: A fast, highly efficient method for storing computer display information (13) which contains both text and graphics (26, 27). The method separates text (26) from graphics (27) compressing, storing each separately to optimize compression. The method allows use of multiple text fonts (21) on the same display (13) and is simple enough for an 8-bit microcomputer.