Abstract: A differential capacitor structure includes a first static conductive layer and a second static conductive layer not electrically coupled to the first static conductive layer. A dynamic conductive layer is suspended between the first and second static conductive layers.

Abstract: A method of fabricating a low voltage, deep junction semiconductor device includes providing first and second wafers of opposite conductivity types, each having a dopant concentration of at least 4.0.times.10.sup.16 atoms/cc. After cleaning the wafers and removing heavy metal impurities therefrom by gettering, the wafers are bonded together. This method results in the successful fabrication of semiconductor devices having a junction depth in the range of 20 to 500 microns and a breakdown voltage of less than 20 volts.

Abstract: A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised of gallium arsenide, is then formed on the interface layer and is followed by the formation of a doped aluminum gallium arsenide layer thereon. A source, a gate and a drain are then formed on the FET layers. The FET and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.

Abstract: A beverage receptacle holder comprises a substantially circular first portion having a first end and a second end and a substantially circular second portion having a first and contiguous to the second end of the first portion and a second end. The first portion is of a first diameter while the second portion is of a second diameter which is larger than the first diameter. This enables the beverage receptacle holder to securely hold cups, glasses, cans, mugs and other beverage receptacles of various sizes.

Abstract: A method of fabricating a semiconductor structure having MOS and bipolar devices includes providing an isolation structure having MOS and bipolar active areas including doped wells. A collector region is formed in the bipolar active area well and a first semiconductor layer is then formed over the MOS and bipolar active areas. An active base region is formed in the bipolar active area well and a dielectric layer is formed on the first semiconductor layer over a portion of the bipolar active area. A window is formed through the dielectric layer and extends to the first semiconductor layer. A second semiconductor layer is then formed over the MOS and bipolar active areas. A gate electrode is formed on the MOS active area and emitter and collector electrodes are formed on the bipolar active area. The gate, emitter and collector electrodes are formed from both the first and second semiconductor layers and the emitter electrode extends into the window.

Abstract: A method for forming high quality oxides wherein semiconductor material is placed in an oxidizing environment and subjected to a predetermined concentration of oxygen. This oxygen concentration is increased over time until a predetermined amount of oxide has been formed. Once the predetermined amount of oxide has been formed, the semiconductor material/oxide interface is subjected to a burst of steam that passivates the interface thereby reducing the number of unreacted semiconductor material atoms.

Abstract: An improved semiconductor die for plastic encapsulated semiconductor device packages which impedes the inherent delamination caused by the differing expansion coefficients of the semiconductor die and plastic encapsulation. Rounded or tapered die corners and die edges decrease the stress from the plastic encapsulation that acts upon the semiconductor die. This reduced stress slows the delamination progression and leaves the operational circuitry unaffected for an increased period of time thereby increasing device lifetime.

Abstract: A method of fabricating heterojunction structures includes providing a semiconductor substrate and forming a plurality of semiconductor layers thereon. Ohmic and gate contacts are then formed on the plurality of semiconductor layers and portions of at least one of the semiconductor layers disposed between the ohmic and gate contacts are removed. Gate metal is then formed on the gate contacts. Source and drain regions are formed in the semiconductor layers and the formation is self-aligned to the gate metal. Following the formation of the source and drain regions, ohmic metal is formed on the ohmic contacts.

Abstract: A method of fabricating a trench structure includes providing a substrate having a first layer disposed on a surface thereof and a second layer disposed on the first layer. A trench is formed through the first and second layers and into the substrate. A dielectric liner is formed on the sidewalls of the trench which is then filled with a trench fill material. Portions of the trench liner disposed above the trench fill material are removed and a conformal layer is then formed on the trench structure. The conformal layer and a portion of the trench fill material are then oxidized.

Abstract: A method of forming planar isolation regions in semiconductor structures includes providing a semiconductor substrate and forming a semiconductor layer thereon. A dielectric layer comprising at least two different dielectric materials is disposed on the semiconductor layer and a trench is etched therethrough and into the semiconductor layer. Dielectric sidewalls are formed in the trench which is then filled by selectively forming depositing polycrystalline silicon therein. The semiconductor material is then at least partially oxidized to form the planar isolation region. The isolation regions disclosed herein may be used for both intradevice and interdevice isolation.

Abstract: A substantially self-sealing episcleral incision having an approximate central point 1.5 to 3.0 millimeters posterior to the limbus. Portions of the incision extending from the approximate central point extend laterally away from the curvature of the limbus. The configuration of the self-sealing incision allows the incision to seal as the eye is inflated following surgery and therefore requires no sutures for sealing. Accordingly, the probability of astigmatism is eliminated or greatly reduced and the reliance on sutures is eliminated.

Abstract: A semiconductor device structure comprises a semiconductor substrate having a semiconductor layer of the same conductivity type formed on its first surface. A drain contact is formed on the second surface of the substrate and conductive regions having the opposite conductivity type of the substrate are formed in the semiconductor layer and are separated by a predetermined distance. Channel regions having the same conductivity type as the substrate are disposed above the conductive regions and source regions are disposed therein. A shielding region is then formed on the surface of the device structure in the area between the conductive regions. The structure allows for reduced or eliminated gate-drain capacitance, reduced output conductance and increased breakdown voltage capability.

Abstract: A method of forming oppositely doped semiconductor regions includes providing a first semiconductor layer of a first conductivity type and forming a second semiconductor layer of a second conductivity type on a portion of the first layer. A third semiconductor layer is formed on the second layer and the exposed portions of the first layer. The dopant concentration of the third layer is less than the dopant concentration of the second layer so that dopant of the second conductivity type diffuses from the second layer into the portion of the third layer disposed thereabove.

Abstract: A vacuum wafer transport and processing system and method includes a central vacuum chamber having wafer holding means disposed therein. A plurality of wafer transport arms are disposed between the central vacuum chamber and a plurality of wafer process chambers. The wafer transport arms transport wafers between the various process chambers and the central vacuum chamber so that multiple processing steps may be performed in a vacuum.

Abstract: A method of fabrication of a device having laterally isolated semiconductor regions. In a preferred embodiment, laterally isolated polysilicon features are created with vertical, nitride-sealed sidewalls. The nitride-sealed sidewalls formed using sidewall spacer technology eliminate oxide encroachment while further preventing the loss of dopant laterally during thermal processing. The final structure comprises polysilicon features flanked by either oxide isolation or additional polysilicon features and is planar without requiring a planarization etchback. The process is applicable to polysilicon electrodes over active areas as well as polysilicon resistors over isolation oxide.

Abstract: A method for electrolessly plating portions of semiconductor devices and the like comprises the steps of providing a first metal having a higher electromotive series than a coating metal, galvanically coupling a second metal to the first metal wherein a portion of the first metal remains exposed and then subjecting the second metal and the exposed portion of the first metal to an electroless coating metal plating solution. The method employs no masks and is ideal for plating small areas such as single ball bonds and limited numbers of ball bonds on a single semiconductor chip.

Abstract: A method of fabricating a semiconductor structure having self-aligned diffused junctions is provided wherein a first dielectric layer, a doped semiconductor layer and a second dielectric layer are formed on a semiconductor substrate. An opening extending to the semiconductor substrate is then formed through these layers. Undoped semiconductor spacers are formed in the opening adjacent to the exposed ends of the doped semiconductor layer and dopant is diffused from the doped semiconductor layer through the undoped semiconductor spacers and into the semiconductor substrate to form junctions therein. This provides for integrated contacts through the doped semiconductor layer.

Abstract: A method of fabricating electrodes comprises providing a semiconductor structure having doped tubs and forming a first dielectric layer of a first dielectric material thereon. A second dielectric layer of a second dielectric material is formed on the first dielectric layer and openings are formed in the second dielectric layer that extend to the first dielectric layer. A conformal semiconductor layer is formed over the entire semiconductor structure and nitride spacers are then formed in the openings on the conformal semiconductor layer. The conformal semiconductor layer is then oxidized so that only semiconductor slivers remain beneath the spacers. The spacers and the semiconductor slivers are removed as well as the portions of the first dielectric layer disposed therebeneath. Conductive electrodes which are coupled to the doped tubs are then formed in the openings.

Abstract: A method of removing an adhered film from a workpiece includes holding a workpiece having a film to be removed adhered thereto in a stationary position. An adhesive is applied along a length of the film that is less than the length of the entire film. Once the adhesive has been applied, it is pulled away from the workpiece so that the film separates from a portion of the workpiece and may then be completely removed therefrom.

Abstract: An external contact method and package wherein one embodiment includes a semiconductor die having a plurality of metallization layers including a top metallization layer that is covered by a passivating layer. At least a portion of the passivating layer is removed to expose at least a portion of the top metallization layer. Once the top metallization layer is exposed, external contact means are press-fit directly into the exposed portion. In a high powered ECL circuit, the present invention eliminates or greatly decreases voltage drop problems along the power bus lines which cause logic errors if the voltage drop is too large.