Abstract: A multichip IC module having dice and substrates coplanarly bonded therein. After the dice are aligned into die openings of the substrate, a glass slurry is applied and the module is fired to solidify the glass. Because of shrinkage of the glass slurry firing, a groove results between the dice and the substrate. To fill on this groove, a polyimide or like film is adhered and then pressued and cured on the surface of the dice and substrate. This film is used as a base for interconnect lines.

Abstract: A process for flashing a thin layer of silver on metal leadframes using no mask steps and a minimal amount of silver. An unmasked metal leadframe is placed into a cleaning bath that includes silver in solution and has no outside electrical driving force to assist plating. The leadframe is removed from the cleaning bath once a uniform silver layer having a thickness of 100 to 1000 angstroms is plated thereon. The silver layer need not be exact and, therefore, it is not critical that the period of time the leadframe remains in the cleaning bath be exact.

Abstract: A semiconductor device having a conductive recombination layer. The conductive recombination layer, comprised of doped polycrystalline material, doped polycrystalline material and tungsten silicide, or tungsten silicide, is disposed between two separate semiconductor substrates which are bonded together using a polished surface on the conductive recombination layer as one of the bonding interfaces. The conductive recombination layer recombines minority carriers and thereby increases the switching speed of the device.

Abstract: A method for removing nitride coatings from metal tooling and mold surfaces without damaging the underlying base metal includes placing the nitride coated metal surface into a plasma reactor and subjecting it to a gaseous plasma comprising a reactive fluorine species. The reactive fluorine species may be derived from one or more of many well known gases. An optional step of cleaning the nitride coating is recommended.

Abstract: A planarized dielectric isolation region for semiconductor devices and integrated circuits is created by providing a semiconductor substrate, providing on the substrate an oxide/nitride mask with an opening for defining the isolation region and a closed portion for defining the desired semiconductor islands, anisotropically etching a trench into the semiconductor substrate, isotropically etching the substrate so as to slightly undercut the oxide/nitride mask, thermally oxidizing the substrate to form a thin oxide layer on the bottom and sidewall of the trench wherein the outer surface of the thermal oxide approximately lines up with the edge of the oxide/nitride mask at the top of the trench sidewall, filling the trench with a conformal deposited material (preferably a dielectric), providing a mask over the conformal material which is the complement to the trench etch or island mask but of smaller lateral dimensions so as to cover those portions of the conformal layer which do not rise up over the semiconduct

Abstract: A process for fabricating complimentary semiconductor devices having pedestal structures wherein both PNP and NPN transistors are formed simultaneously on the same substrate. After polysilicon layers have been patterned and etched, various polysilicon regions are doped with a plurality of conductivity types. This allows for there to be both P+ and N+ regions in the same polysilicon layer thereby enabling complimentary PNP and NPN transistors to be formed using a limited number of processing steps.

Abstract: A low capacitance, high performance semiconductor device is described having a sidewall emitter wherein the emitter width is relatively small (approximately 0.5 micrometers). This enables a small emitter-base interface which reduces capacitance. Additionally, the regions of the base and collector near their interface are lightly doped so that collector-base capacitance is greatly reduced.

Abstract: A method for the selective deposition of metals in semiconductor device manufacturing wherein a wafer surface is subjected to a hydrogen species that reduces oxidation on conducting materials while also removing impurities from non-conducting materials. Metals are then selectively deposited upon the conducting materials and not upon the non-conducting materials. It should be understood that the hydrogen treatment step and the selective metal deposition step may be performed simultaneously or by using two separate processing steps.

Abstract: A light diffuser is described having a body with an opening therethrough defined by an inner wall. Light conducting paths are disposed through the body and couple to the opening. The inner wall is sloped at an angle to reflect the light onto a workpiece. The size of the opening and the height of the diffuser above the workpiece determine the angle of the inner wall.

Abstract: A metallization process for semiconductor devices wherein the metal deposition steps are performed at higher wafer temperatures than subsequent processing steps. The correlation between wafer temperature and maximum grain width is prevalent in many metals used for semiconductor device metallization such as aluminum. Therefore, by measuring and controlling the maximum grain width of the deposited metal during metal deposition steps, it is possible to control and adjust the wafer temperature.

Abstract: A semiconductor device having a conductive recombination layer. The conductive recombination layer, comprised of doped polycrystalline material, doped polycrystalline material and tungsten silicide, or tungsten silicide, is disposed between two separate semiconductor substrates which are bonded together using a polished surface on the conductive recombination layer as one of the bonding interfaces. The conductive recombination layer recombines minority carriers and thereby increases the switching speed of the device.

Abstract: A semiconductor die for plastic encapsulation having an adhesion promoter selectively disposed on an outer surface enabling better adhesion between the semiconductor die and a plastic encapsulation. The improved adhesion allows for less relative motion between the semiconductor die and the plastic encapsulation. The reduction of relative motion significantly decreases the delamination progression throughout the semiconductor device and allows for an increased semiconductor device lifetime.

Abstract: An automated curing oven system for use in the manufacturing of semiconductors. This system may easily be incorporated with other automated machinery used for various semiconductor processing steps because it employs the same device holding magazine used for many other steps. The device holding magazine serves as the oven chamber itself thereby eliminating many manual handling steps.

Abstract: Described herein is a standoff for use with semiconductor packages to prevent chipping. The standoff is designed to fit over a pin of the package and seat on the package surface with a portion extending over the corner of the package.

Abstract: A diode having an increased diode voltage drop is provided through the use of an extra collector-base contact which is left electrically floating. By leaving the extra collector-base contact electrically floating, a voltage divider effect results which provides an increased voltage drop across the diode without requiring other structural changes nor increased diode current.

Abstract: A flip chip module including a film having solder receptor pads and interconnect lines to which a plurality of electronic devices and the like are bonded. The film is folded at predetermined areas thereby decreasing the size of this multichip device. A removable heat radiating cover is disposed over the film. This cover allows for both heat dissipation and easy access internal components for both testing and replacement after the flip chip module has been assembled.

Abstract: A vertical III-V compound MESFET is provided. The MESFET has a buried P-type layer which separates the source and the drain regions. A small N-type region in the buried P layer connects the source channel to the drain area. This opening in the buried P layer is located underneath the Schottky gate.

Abstract: A method for making a bipolar semiconductor device having silicide contacts which is compatible with the processing steps used in the fabrication of MOS devices. The present invention includes the use of sidewall spacers to limit the self-aligned implants of the extrinsic base and the silicide contact. The device is annealed so that the diffusion of the polysilicon layer which forms the emitter may be controlled. Since the emitter size may be controlled, the emitter to base contact area may be reduced resulting in improved device performance.

Abstract: A three dimensional interconnected modular integrated circuit and method of manufacturing same are provided wherein the modular circuit comprises individual planar integrated circuits which are connected together and to an interconnect chip for mounting on a lead line package resulting in an increase in available integrated circuit surface area for a given footprint area.

Abstract: A method for bonding die to substrates coplanarly in a multichip module assembly. After the die are aligned into die openings of the substrate, a glass slurry is applied and the module is fired to solidify the glass. Because of shrinkage of the glass slurry firing, a groove results between the die and the substrate. To fill on this groove, a polyimide or like film is adhered and then pressed and cured on the surface of the die and substrate. This film is used as a base for interconnect lines.