Abstract: A system of transmitting computer display information as facsimile pels through conventional facsimile machines. The system comprises a conversion means for scaling each dot of display into facsimile pels using a scaling factor which is used to scale both the width and height of each dot of display. Each dot of display is output as some whole number of facsimile pels. Given that many facsimile machines have no memory, the facsimile pels are temporarily stored as encoded data and output in a steady stream of data bits to the facsimile machine. This frees up the limited memory of the MCU of the pocket size computer.

Abstract: An output driver (100) for driving an external impedance load (160) comprising an output stage (110) and an impedance element (120). An input signal to the output stage (110) is controlled to provide an output signal that then drives the external impedance load (160).The output stage (110) comprises an input controller (112) that couples to a current generator (114) and a current replicator (116). A voltage reference source (150) determines a quiescent output current level of the current generator (114). The impedance element (120) comprises a current modulating resistor (230) that couples a two polarity voltage supply (130) to the output stage (110).Operations of the output driver (100) depends on the external load impedance (160). For a high external impedance load, the output driver (100) functions as a simple voltage follower.

Abstract: Self-aligned HFETS are fabricated by providing a semi-insulating substrate and forming a low bandgap III-V semiconductor layer thereon. A first dielectric layer of a first dielectric material is formed on the III-V layer and first and second openings are formed through the first dielectric layer and the III-V layer. After forming dielectric spacers of a second dielectric material on the sidewalls of the first and second openings, gates are formed therein. The first dielectric layer is subsequently removed and source and drain regions are formed in the III-V layer and substrate adjacent to each of the gates. The formation of the source and drain regions is self-aligned to the gates. After forming isolation regions between devices, ohmic contacts to the source and drain regions, all being of a like material, are formed. This formation is also self-aligned to the gates.

Abstract: A method for determining test pattern fault equivalence. The method comprises selecting a bridging fault (16) from a digital circuit, then determining a stuck-at fault (17) which guarantees detection of the bridging fault. Generation of a test vector (18) which detects the stuck-at fault. Simulating the test vector (19) to find all bridging faults that are detected by the test vector, and repeating the above steps until the desired percentage of detectable bridging faults are examined.

Abstract: A method of etching a semiconductor wafer includes providing a wafer having a portion thereof to be etched. A highly doped region is formed in the periphery of the wafer which is subsequently etched. The highly doped region of the wafer is substantially etch resistant to an etchant relative to the portion of the wafer being etched.

Abstract: A circuit including an operational amplifier (A) having an input stage comprising first and second transistors (10, 12) coupled in differential configuration and being powered by a first current source (20), the current source being powered by the output of the operational amplifier, wherein in order to ensure start up of the amplifier a second current source (34) is coupled to the differential pair of transistors, wherein a sensing means (40, 42) is provided responsive to the inputs of the operational amplifier and arranged to control energization of the second current source in order to switch off the second current source after switch on of the amplifier.

Abstract: A voltage converting circuit receiving an input voltage and an increased voltage and providing an output voltage higher than the input voltage at an output terminal, comprises a first pair of gate devices serially connected between the input voltage and a ground, a second pair of gate devices serially connected between the input voltage and the output terminal, a first capacitor connected between a node between the first pair of gate devices and a node between the second pair of gate devices for boosting the output voltage, a second capacitor connected between the output terminal and the ground for smoothing the output voltage, a control circuit for controlling said pairs of gate devices, and a pair of drivers for driving the second pair of gate devices respectively under the control of the control circuit. The pair of drivers are connected so as to operate between the increased voltage and the input voltage.

Abstract: A discriminator device for discriminating between two types of signal applied to an input port (EN), the first type being a binary logic signal having high and low values, and the second type of signal being a continuously variable signal or a floating voltage, the device including a voltage divider network (R1,R2) for coupling to the input port and a voltage supply (VCC) in order to provide a format signal, a second voltage divider network (R3,R4,R5) providing first and second voltage reference signals (VR1,VR2) having values intermediate the high and low values of the binary logic signal, comparators (34A, 34B) coupled to receive the format signal and the voltage reference signals, the outputs of the comparators being coupled to an output logic circuit (36-39) which provides a logic output signal of a value depending on the type of signal present at the input port.

Abstract: A lock detection circuit (2) for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal (REFERENCE). The lock detection circuit includes a circuit for generating first (UP) and second (DOWN) pulses, the first and second pulses respectively representing positive and negative differences between a parameter, such as phase, of the PLL signal and a parameter of the reference signal, and a first counter (4) for counting sets of first and second, pulses, each set comprising a first pulse followed by a second pulse, the first counter on counting a predetermined number of sets of pulses providing a first count complete signal.

Abstract: A superluminescent surface light emitting device comprising a mirror layer (19) formed on a surface of a semiconductor substrate (22). Above the mirror (19) is a light emitting region (16). A second mirror (12) is located in a plane above the light emitting region (16). The combined reflectivities of the mirrors (19,12) are selected such that light is emitted in the superluminescent operating mode in a direction perpendicular to the surface of the device. An implanted region (14) may be used to improve superluminescent operation.

Abstract: Optimization of test stimulus verification by analyzing test stimulus timing information against restriction rules derived from a static analysis of a digital system. The result of this analysis is used to determine test stimulus timing which cannot cause a timing violation and to remove the associated vectors from further checking. Only those vectors which can violate timing constraint rules are checked individually to find states which violate the timing rules.

Abstract: A semiconductor package includes a die having a first surface including a plurality of bond pads disposed thereon and a second surface. Inner lead portions of a TAB leadframe are coupled to the bond pads and outer lead portions electrically coupled to the inner lead portions extend therefrom. An encapsulation is disposed on the first surface of the die including the bond pads having the inner lead portions of the TAB leadframe bonded thereto. Encapsulation is also disposed about the sides of the die. The second surface of the die remains exposed. This allows for a relatively thin package having superior thermal dissipation properties.

Abstract: A method of processing a semiconductor device in which a microwave field is generated to surround the semiconductor device while a focussed electron beam or ion beam is applied to the substrate of the device whereby the presence of the electron or ion beam creates a conductive region which increases the microwave field intensity in that region, so that the intensified microwave field creates a local heating effect in the substrate to perform a local annealing action.

Abstract: A semiconductor structure having an edge termination feature wherein at least one guard ring is disposed in a substrate between a main device portion and the edge of the substrate. A dielectric layer is then disposed on the substrate and a plurality of diodes are disposed on the dielectric layer above the at least one guard ring. The at least one guard ring and the diodes are electrically coupled so that the potential of the guard rings may be fixed by the diodes and leakage is greatly reduced.

Abstract: A method of fabricating a resistive conductive pattern on an aluminum nitride substrate includes forming a resistive chromium containing film on the aluminum nitride substrate and then forming a refractory metal layer on the resistive film. The resistive film and refractory metal layer are then patterned and one or more conductive layers may then be formed on the patterned refractory metal layer. Resistors may then be formed between conductive lines patterned from the layers. These resistors are formed from the resistive film.

Abstract: A method of fabricating a semiconductor structure includes providing a substrate having at least one layer formed thereon. At least two trenches are formed through the layer and into the substrate wherein at least one trench is for isolation and at least one trench is for making contact to the substrate. After a trench liner is formed on the sidewalls of the trenches, the trenches are filled with doped semiconductor material. The doped semiconductor material in the trench for isolation is then anodized. After the anodization, the anodized trench fill material is oxidized.

Abstract: A method of anisotropically etching single crystal silicon includes providing single crystal silicon to be etched and placing it in an etching solution consisting essentially of R.sub.4 NOH and solvent wherein R is an alkyl group having between 0 and 4 carbon atoms. The solution will preferentially etch <100> or <110> oriented single crystal silicon. Additionally, electrochemical etching may be employed to preferentially etch P type single crystal silicon.

Abstract: A method of fabricating a CMOS structure that may be integrated into a BICMOS process flow includes forming N and P type doped wells in an isolation module. A first conformal nitride layer is formed on the surface of the isolation module and portions of the nitride layer disposed over the doped wells are removed. After forming a gate oxide layer on the doped wells, a conformal polysilicon layer is formed and doped on the surface of the structure. The conformal polysilicon layer is etched into gate electrodes which are used as a mask for the self-aligned implant of first portions of source and drain regions in the doped wells. Dielectric spacers abutting the edges of the gate electrodes are formed and the implantation of second portions of the source and drain regions is self-aligned to the dielectric spacers. Following the formation of a conformal nitride layer and a conformal oxide layer, the structure is planarized and source, drain and gate contacts are formed.

Abstract: A surge suppressor semiconductor structure includes a semiconductor substrate of a first conductivity type and an epitaxial semiconductor layer of a second conductivity type disposed thereon. A region in the epitaxial layer has a higher dopant concentration than the remainder of the epitaxial layer. This creates a junction at an interface of the substrate and the highly doped region of the epitaxial layer. A moat is disposed about the epitaxial layer and a portion of the substrate and dielectric material is disposed in the moat and on the epitaxial layer. Contacts are then formed to contact both the highly doped region of the epitaxial layer and the substrate.

Abstract: An electrolytic process employing a water solution of metal lactates or lactic acid and metal hydroxides, rapidly and safely removes metal plating bleed, residual oxides or the like (stains), plastic flash, resin bleed and deflashing media, from electrodes of electronic devices. Anodic etching or a combination of cathodic and anodic etching is preferred. Noble metals are selectively removed without cyanide compounds. For example, excess silver from spot plating on copper leadframes is etched away 2-3 times faster than the underlying copper. After cleaning the device leads are bright, polished, stain-free and without scale, residual plating bleed, deflashing media, plastic flash or resin bleed. The process is effective, less hazardous, easy to use and economical.