Abstract: An exercise system includes a local system having an exercise apparatus and an associated local computer, where the local computer controls and monitors the operation and use, respectively, of the exercise apparatus. The system further includes a remote system having a remote computer, and a transmission medium including a telephone line that couples the local system to the remote system for data communication between the local system and the remote system. The remote system may receive local system data from the local system concerning the use of the exercise apparatus, and the local system may receive remote system data from the remote system concerning the operation of the exercise apparatus. The local computer preferably controls the operation of the exercise apparatus based upon a modifiable script stored in a read/write memory of the local computer, which can be updated by the remote system.

Abstract: A lapping guide for use in fabrication of a device includes a first resistive element and a second resistive element. The two resistive elements can provide different changing resistances throughout the lapping of the device. These two resistances can be used throughout the lapping of the device to facilitate determination of when a predetermined desired height of the device has been achieved, and therefore stop the lapping of the device. The resistive elements can be physically adjacent to each other or separate from each other. Further, a common lead can be electrically connected to both resistive elements for measuring their respective resistances. In addition, the resistive elements can be separated from each other by the device.

Abstract: An inductive write head includes a first pole and a second pole that form a yoke having a write gap between the first pole and second pole. The second pole is formed of a particular Co100-a-bZraCrb compound. More specifically, the second pole is formed where “a” is in the range of about 2 atomic percent to about 18 atomic percent, and “b” is in the range of about 0.5 atomic percent to about 6 atomic percent. The magnetic write element also includes a conductive coil which lies between the first pole and the second pole. The inductive write head also includes a first yoke pedestal attached to the first pole, and a second yoke pedestal attached to the second pole, with the write gap formed therebetween. Further, the first yoke pedestal has a pedestal width that defines the write element trackwidth and that is smaller than the pedestal width of the second yoke pedestal.

Abstract: An improved method for specifying and reliably detecting endpoints in processes such as plasma etching, where the signal-to-noise ratio has been severely degraded due to factors such as “cloudy window” and low ratio of reactive surface area to non-reactive surface area. The improved method of the invention samples signals produced by photo sensitive equipment, digitally filters and cross-correlates the data, normalizes the data using an average normalization value, and provides further noise reduction through the use of three modes of endpoint specification and detection. The three modes of endpoint specification and detection require a pre-specified number of consecutive samples to exhibit a certain behavior before the endpoint is deemed detected and the process terminated as a result. The three modes of endpoint specification and detection also permit a very fine control of the etch time by permitting the user to adjust the specified endpoint by gradations of the sampling period.

Abstract: A process is disclosed for making grids for flat-panel displays. The screen grids are coated with non-evaporable getter materials and the metal sheet forming the grid is coated with a coating that is as thick as the resulting grid and having at least the same surface area as the image formation zone of the flat-panel display. At least one side of the grid is coated with one or more non-evaporable getter materials and then parts of the sheet thereby coated are selectively removed. Some embodiments of grids produced with such a process are also disclosed.

Abstract: The present invention teaches a variety of transconductance circuits formed having a class AB transconductor amplifier coupled in parallel with at least one concave compensation circuit. When the transconductance circuit has only one concave compensation circuit, the concave compensation circuit is designed with no offset so that the concave transconductance gain of the compensation circuit compensates for the convex transconductance gain of the class AB amplifier thereby providing a more linear transconductance circuit. When the transconductance circuit includes multiple concave compensation circuits, they each are designed with an offset chosen such that the combination of the individual concave transfer functions achieve a more linear transconductance circuit.

Abstract: Disclosed is a differential amplifier including an emitter follower pair, a first differential pair, and a main differential amplifier. The emitter follower pair is operative to receive an input differential voltage signal for shifting the input differential voltage signal to develop a shifted differential voltage signal. The first differential pair is configured to feed a first differential current inversely to the emitter follower pair so that a transconductance of the emitter follower pair changes inversely to compensate for a change in a transconductance of the first differential pair. The main differential amplifier is coupled to receive the shifted differential voltage signal and is configured to amplify the shifted differential voltage signal to generate an output voltage signal.

Abstract: A MOS gate manufacturing operation is capable of preventing acid corrosion and station contamination. The manufacturing method includes the steps of sequentially forming a polysilicon layer, a barrier layer, a silicide layer and a cap layer over a silicon substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the barrier layer. Finally, the substrate is cleaned following by the formation of a source/drain region having a lightly doped drain structure on each side of the gate. The thin oxide layer is capable of protecting the barrier layer against acid corrosion without causing any noticeable increase in gate conductivity.

Abstract: An amusement toy including a head having at least a partial facial image, and an elastically deformable mouth associated with the head. The mouth has an undeformed dimension in the absence of a deforming force and is capable of deforming such that a deformed dimension of the mouth is at least 20% greater than the undeformed dimension of the mouth. The deformation of the mouth of the toy alters the facial image presented by the head, making a “scary face.” The removal of the force causes the mouth to return to substantially its undeformed dimension. A body of the amusement toy is preferably attached to the head such that the center of gravity of the toy is below the elastically deformable mouth.

Abstract: A method of dual damascene includes forming a first conducting layer on a substrate, which already contains formed devices, and then forming a first dielectric layer and a hard material layer on the first conducting layer. The hard material layer contains a first opening, which is located right over the first conducting layer. A second dielectric layer is formed on the hard material layer, wherein the second dielectric layer is enforced by a ion implantation process or a plasma process. A hard mask layer containing a second opening is then formed on the second dielectric layer, wherein the second opening gradually widens upward, and wherein the second opening is located over the first opening. The hard mask layer is then used to pattern the second dielectric layer to expose the hard material layer. A part of the first dielectric layer is removed to expose the first conducting layer and form a third opening after a protection layer is formed on the side wall of the second dielectric layer.

Abstract: The present invention teaches a variety of output stages for amplifying high speed signals while keeping distortion low and using a low supply voltage. The invention includes the use of dual complementary signal paths that include a complementary push-pull output stage. Bias circuits are used to keep the paths symmetrical and positive feedback is used to oppose output loading effects.

Abstract: A method of fabricating a one-time programmable read only memory (OTP-ROM) with reduced size is disclosed. In accordance with the method of the present invention, a stacked structure is formed on a substrate. The stacked structure comprises a first oxide layer, a first polysilicon layer, and a second oxide layer formed in sequence on the substrate. The substrate beside the stacked structure is exposed by the stacked structure. An implanted region is formed in the exposed substrate beside the stacked structure. A spacer is formed on a sidewall of the stacked structure. A silicide layer is formed on the implanted region. A silicon nitride layer is formed to cover the second oxide layer, the spacer, and the silicide layer. A second polysilicon layer is formed to cover the silicon nitride layer. The second polysilicon layer is patterned to form a control gate. The first polysilicon layer is further patterned to form a floating gate.

Abstract: A virtual computer monitor is described which enables instantaneous and intuitive visual access to large amounts of visual data by providing the user with a large display projected virtually in front of the user. The user wears a head-mounted display or holds a portable display containing a head-tracker or other motion tracker, which together allow the user to position an instantaneous viewport provided by the display at any position within the large virtual display by turning to look in the desired direction. The instantaneous viewport further includes a mouse pointer, which may be positioned by turning the user's head or moving the portable display, and which may be further positioned using a mouse or analogous control device. A particular advantage of the virtual computer monitor is intuitive access to enlarged computer output for visually-impaired individuals.

Abstract: The present invention teaches a variety of transconductance circuits formed having two or more class AB transconductor amplifiers coupled in parallel. The class AB transconductor amplifiers have non-linear voltage to current transfer functions and are each designed with an offset chosen such that the combination of the individual nonlinear transfer functions achieve a more linear transconductance circuit.

Abstract: A dilution reservoir (10) with one or more channels (30) is provided in which the channels (30) are easily accessible and which allow improved material manipulation. The dilution reservoir (10) includes a housing (14), having a base (18), a top (16) opposite the base (18) and a plurality of sides (20), (22). One or more channels (30) are located in said housing (14), each channel (30) having a mouth (40) at the top (16) of the housing (14) which opens into a cavity (38). Each channel (30) and each cavity (38) has a longitudinal axis (44), a transverse axis (48), a depth axis (46), and the channels (30) have arcuate cross-sections. These arcuate cross-sections provide true low points (60) in the bottom (56) of each cavity (38) which facilitate collection of material. The mouths (40) of the channels (30) are elongated in the direction of the longitudinal axis (44) thus allowing a wider range of access angles (78) for insertion of a standard pipettor.

Abstract: The present invention provides an improved method of forming a dual damascene structure. Patterns of a metallic trench and a via hole are formed by using the photolithography process twice. After the first etching step of the dielectric layer the first photoresist layer is not removed. Thus, the first photoresist layer is used with the second photoresist layer as masks in the second etching step of the dielectric layer. The self-aligned method of forming a dual damascene structure thus is provided. In addition, a titanium layer or a titanium nitride layer can be formed on the dielectric layer after the first etching step of the dielectric layer and is used as an anti-reflection layer.

Abstract: A method for forming a contact hole in a silicon oxide layer formed over a silicon nitride layer and a substrate performs an etching process with an etchant, C4F8/Ar or C4F8/C2F6/Ar, on an inductively coupled plasma etcher. The inductively coupled plasma etcher contains a chamber, a ring, and a roof. The etchant used in the etching process is controlled by conditions that include a C4F8 flow of about 10 to 20 sccm, a CO flow of less than about 100 sccm, and an Ar flow of about 50 to 500 sccm. In the meantime, the conditions of the inductively coupled plasma etcher include a roof temperature of about 150 to 300 ° C., a ring temperature of about 150 to 400 ° C., and a pressure within the chamber of about 4 to 50 mtorr. By performing a plasma etching process under the foregoing conditions, a properly profiled contact hole is obtained.

Abstract: The present invention teaches a power amplifier having two output power devices and a mechanism for switching the output path between these two power devices. The first output power device is designed for power efficient signal amplification at the power amplifier's highest output power level. The second output power device is designed for power efficient signal amplification at the output power level that the power amplifier is most likely to operate. By switching between the two power devices according to the output power level, a high level of power efficiency can be achieved across a broad range of operating states of the power amplifier.

Abstract: A method of manufacturing a salicide layer is described. A substrate having a memory region and a logic circuit region is provided, wherein the memory region comprises a first gate structure and a first source/drain region and the logic circuit region comprises a second gate structure and a second source/drain region. A first salicide layer is formed on the second gate structure and the second source/drain region in the logic circuit region. A dielectric layer is formed over the substrate. A portion of the dielectric layer is removed to expose the first gate structure and the first salicide layer above the second gate structure. A second salicide layer is formed on the first and the second gate structure.

Abstract: A manufacturing method is capable of preventing corrosion of a metal oxide semiconductor. The manufacturing method sequentially forms a polysilicon layer, a silicide layer and a top cap layer over a substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the silicide layer. Finally, the substrate is cleaned, and then of a source/drain region having a lightly doped drain structure is formed on each side of the gate.