Abstract: A magnetoresistive device for recording data includes a first pole connected to a second pole that is above the first pole. Above the first pole is a first conductive coil imbedded in a first insulation material, with at least a portion of the first conductive layer disposed below all of the second pole. The first and second poles have a first and second pole tip portion, respectively, between which is defined a write gap. A first pole pedestal, connected to the first pole at the first pole tip portion, and a second pole pedestal, connected to the second pole at the second pole tip portion, can be located between the first and second poles. Also, additional conductive coils can be included above the first conductive coil.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is provided. The method has steps of sequentially forming an oxide layer, a polysilicon layer and a cap layer on a semiconductor substrate to form a first-stage gate. An interchangeable source/drain region with a lightly doped drain (LDD) structure is formed in the substrate at each side of the first-stage gate. An insulating layer is formed over the substrate, and is planarized so as to exposed the cap layer. Removing the exposed cap layer forms an opening that exposes the polysilicon layer. Using the insulating layer as a mask, a self-aligned selective local implantation process is performed to form a threshold-voltage doped region and an anti-punch-through doped region below the oxide layer in the substrate. A conductive layer is formed over the substrate to fill the opening.

Abstract: A method for forming an amorphous silicon layer over the terminals of a MOS transistor. The method includes the steps of forming a mask layer having an opening that exposes the gate polysilicon layer over the MOS transistor. Next, using the mask layer as a mask, an inactive ion implant operation is carried out such that inactive ions are implanted into the gate polysilicon layer. Thereafter, again using the mask layer as a mask, a first heavy bombarding operation is carried out, implanting ions locally. Finally, the mask layer is removed and then a second heavy bombarding operation is carried out, implanting ions globally.

Abstract: A method and apparatus for controlling the amount of row distortion before and dynamically during the lapping process used to manufacture sliders for magnetic storage devices. A wafer quadrant of slider rows is bonded to an extender tool held in a carrier assembly and an actuator is used to laterally apply force to the extender tool such that it changes the profile of the wafer quadrant, and thus the foremost slider row. Multiple arms may be defined in the extender tool, permitting independent engagement with and application of the lateral force by the actuator. Bending moments in each arm are then efficiently and controllably transferred into a beam in the extender tool which is proximate to the point where the wafer quadrant is bonded.

Abstract: A method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. The dielectric film can be a mono-layer structure or a multi-layer structure comprising various dielectric materials. A rapid thermal process (RTP), such as a rapid thermal annealing, or a plasma treatment is performed to enhance the quality of the dielectric film. A photolithography and etching process is performed to remove a part of the dielectric film and the first metal layer to expose a part of the inter-layer dielectric layer. The remaining first conductive layer is used as a lower electrode. A conventional interconnect process is performed on the exposed inter-layer dielectric layer and on the dielectric film. For example, a glue layer is formed on the exposed inter-layer dielectric layer and on the dielectric film. A second metal layer is formed on the glue layer.

Abstract: A cluster computer system including multiple network accessible computers that are each coupled to a network. The network accessible computers implement host computer programs which permits the network accessible computers to operate as host computers for client computers also connected to the network, such that input devices of the client computers can be used to generate inputs to the host computers, and such that image information generated by the host computers can be viewed by the client computers. The system also includes a cluster administration computer coupled to the multiple network accessible computers to monitor the operation of the network accessible computers.

Abstract: A regulating system (10) for a charge pump (12) employing a detection sub-circuit (28) and an enable sub-circuit (30) to operate an oscillator (26) and a channel-switching sub-circuit (32) in an automatic manner producing many of the advantages of previously unreconcilable skip mode and constant frequency mode type regulation. The detection sub-circuit (28) compares a feedback signal (52) from the output terminal (18) of the charge pump (12) to a reference signal (56) and produces an error signal (42) representative of output voltage deviation. Concurrently, the enable sub-circuit (30) compares a threshold signal (72) set for a minimum energy quanta which it is efficient for the flying capacitor (24) of the charge pump (12) to transfer to the error signal (42) and produces an enable signal (38) to enable the oscillator (26).

Abstract: A current mode transmitter is provided including a charge circuit connected to an enable node and adapted to generate a charge current upon the receipt of an activation signal at the enable node. Also included is a discharge circuit connected to the enable node and adapted to generate a discharge current upon the cessation of the receipt of the activation signal at the enable node. An output circuit is connected between an output node and the charge and discharge circuits. The output circuit serves for generating an output current at the output node in response to the charge current and the discharge current. Such output current is initiated within a first delay after the detection of the activation signal by the charge circuit. Further, the output current is terminated within a second delay after the detection of the cessation of the receipt of the activation signal by the discharge charge circuit.

Abstract: An IR transceiver module includes a lead frame, a sensor, an emitter, and a body encapsulating the sensor and emitter, where the body has an integrally formed lens aligned with both the sensor and with the emitter. The sensor is supported proximate to a support surface of the lead frame and has a sensing area which is generally parallel to the support surface. The emitter is supported proximate to the sensor and within a vertical projection of the sensing area, i.e. it is vertically aligned with the sensor. In embodiments of the invention, a recess is formed into the sensing surface of the sensor that is provided with a reflective material to form a reflective cup for the emitter. In other embodiments, a transceiver is also supported proximate to the lead frame and is electrically coupled to both the sensor and the emitter. By providing a module having both the emitter and sensor aligned with a single lens, a very small form factor can be achieved.

Abstract: A gas purification system includes a gas purification unit and one or more safety devices. The gas purification unit includes an enclosure containing a purification material that exhibits an exothermic reaction when exposed to certain gas contaminants. The gas purification unit also has an inlet coupled to an unpurified gas inlet line and an outlet coupled to a purified gas outlet line. A safety device can be coupled either to the unpurified gas input line or the purified output line, or both, and develops an alarm signal when gas contaminants exceed a given concentration level for a period of time.

Abstract: A wafer handling and testing apparatus and method include a station for supporting a wafer carrier, such as a cassette or pod, that holds one or more wafers, where the carrier can be moved in a z-direction. A wafer handling assembly is moveable in an x-direction and removes a wafer from the wafer carrier. The handling assembly includes an end effector and a sensor for detecting an edge of the wafer. A chuck includes a platform that is movable in a z-direction and is used to lift the wafer from the handling assembly and rotate the wafer so that the sensor maps the edge of the wafer. The wafer is then centered on the platform, lowered onto the chuck, and is tested by a test head that is preferably coupled to the handling assembly.

Abstract: An exposure has at least two wafer pads for holding wafers at the same time to perform different tasks including exposing a wafer, aligning a wafer, and loading or unloading a wafer synchronously. The exposure of the invention includes an exposing unit, a wafer supporting unit and a alignment beam scan unit. The wafer-supporting unit contains at least two wafer pads for holding wafers. The alignment beam scan unit contains an interferometer for detecting the interference patterns formed by the alignment beams and the alignment marks on the wafers. The tasks of aligning a wafer, and exposing a wafer, or loading/unloading a wafer can be performed on the wafers placed on each individual wafer pad synchronously.

Abstract: A cascade-type chip module. A laminate substrate having contacts is provided. Chips suitable for the cascade-type module are provided. Each chip includes a redistribution layer having a first region and a second region and bump contacts over the redistribution layer. A layout of the bump contacts coupling with the first region of the redistribution layer is an image rotationally symmetrical to the layout of those coupling with the second region of the redistribution layer, and each of the bump contacts coupling with the first region is coupled with a corresponding bump contact coupling with the second region through the redistribution layer. The chips are divided into a first group and a second group; the first group is stacked on the second group such that the first region of each chip of the first group is aligned with the second region of each chip of the second group and the second region of each chip of the first group is aligned with the first region of each chip of the second group.

Abstract: A method of forming a dual cylindrical capacitor on a semiconductor substrate having at least a device isolation structure and a transistor thereon is provided, wherein the transistor includes at least a gate and a source/drain region. A first insulation layer and a second insulation layer are formed on the substrate. An opening comprising an lower part penetrating through the first insulation layer and an upper part penetrating through the second insulation layer is formed to expose the source/drain region. A conductive layer is formed on the second insulation layer to fill the lower part of the opening and to cover a surface of the upper part of the opening. A spacer is formed on a part of the conductive layer on a side wall of the larger opening. A conductive spacer is formed on the spacer. The spacer is removed.

Abstract: A method of fabricating a static random access memory. A substrate having a gate is provided. A source/drain region is formed in the substrate beside the gate. A metal silicide layer is formed on the source/drain region and the gate region. A conductive line which is electrically coupled to the metal silicide layer on the source/drain region is formed over the substrate. A dielectric layer having a via is formed over the substrate. A portion of the conductive line is exposed by the via. A polysilicon conductive line is formed conformably to the via and the dielectric layer. The polysilicon conductive line is electrically coupled to the conductive line. An ion implantation is performed to form a poly load of the static random access memory.

Abstract: A wafer processing system including a processing chamber, a low pressure pump coupled to the processing chamber for pumping noble and non-noble gases, a valve mechanism coupling a source of noble gas to the processing chamber, an in situ getter pump disposed within the processing chamber which pumps certain non-noble gases during the flow of the noble gas into the chamber, and a processing mechanism for processing a wafer disposed within the processing chamber. Preferably, the in situ getter pump can be operated at a number of different temperatures to preferentially pump different species of gas at those temperatures. A gas analyzer is used to automatically control the temperature of the getter pump to control the species of gasses that are pumped from the chamber.

Abstract: The present invention teaches a variety of methods and systems for providing computer/human interfaces. According to one method, the user interfaces with an electronic device such as a computer system by engaging a sensor with desired regions of an encoded physical medium. The encoded physical medium is preferably chosen to provide intuitive meaning to the user, and is thus an improved metaphor for interfacing with the computer system. Suitable examples of the encoded physical medium include a data-linked book, magazine, globe, or article of clothing. Some or all of the selected regions have had certain information encoded therein, information suitable for interfacing and controlling the computer system. When the user engages the sensor with a region having certain encoded information, the certain encoded information is interpreted and an appropriate action taken. For example, the sensor or the computer system may provide suitable feedback to the user.

Abstract: The present invention teaches output stages having distortion performance improved relative to prior art class-AB output stage distortion performance. The general concept is to constantly bias the feed-forward circuitry of the output stage into a low-distortion operating state. This can be done through several different methods, each of which has its own particular circuit requirements. For example, in one embodiment the bias circuitry generates a near constant bias current suitable for forcing the feed-forward circuitry into a low-distortion operating state regardless of the output stage output value.