Abstract: A high-speed and low-noise output buffer with a slew control function in coordination with a GTL+ signal specification according to the invention. In the output buffer, general and speed driving elements concurrently drives a last output element. As an input signal is changed from a first logic level to a second logic level, the general and speed driving elements simultaneously start functioning. First, the speed driving element pulls down the control voltage of the output element to a potential having a potential difference from an expected final potential. Then, the general driving element pulls down the control voltage to close to the expected final potential. The output potential of the output element changes more quickly at the beginning. When close to the expected final potential, the variation of the output potential slows down.

Abstract: A repairable multi-chip module which is used when failures are found after an electrically and functionally testing is described. A substrate is provided. At least a first normal die having a plurality of first pads is mounted on the substrate, wherein the first normal die is surrounded by the pads. At least a failed die is mounted on the substrate. Several third pads and fourth pads are mounted on the substrate, wherein the third pads surrounds the first normal die and the failed die and the fourth pads surrounds the first pads. At least a second normal die having a plurality of second pads is stacked over the failed die. Several conductive wires are electrically connecting the first pads on the first normal die and the third pads. Several reworking conductive wires are electrically connecting the second pads on the second normal die and the fourth pads.

Abstract: A protocol translation cable assembly includes a first connector having a first plurality of pins, a second connector having a second plurality of pins, and an electrical cable coupling the first connector to the second connector, where the electrical cable includes a plurality of conductors. The protocol translation cable assembly further includes translation circuitry coupled to at least some of the plurality of wires of the electric cable at points between the first plurality of pins of the first connector and the second plurality of pins of the second connector. The translation circuitry preferably derives its power from the electrical cable such that separate power supplies are not required. The cable assembly therefore provides transparent "plug-and-play" capabilities.

Abstract: An apparatus and a method of forming a thick polysilicon layer are provided. An additional pipeline is introduced into a chamber that is used for depositing polysilicon layers. A thin silicon dioxide film is formed using oxygen after forming a first doped polysilicon layer with a constant thickness. Then a second doped polysilicon layer with a constant thickness is deposited on the thin silicon dioxide layer. The steps described above are repeated until a desired thickness is attained.

Abstract: A digital protocol translator including a first protocol circuitry having a first I/O port adapted to communicate using a first digital protocol, the first protocol circuitry including a first controller. The translator further includes a second protocol circuitry having a second I/O port communicating using a second digital protocol different from the first digital protocol, the second protocol circuitry including a second controller in communication with the first controller, such that communications between the first I/O port and the second I/O port are translated between the first protocol and the second protocol. Preferably, the translator further includes a microprocessor and digital memory, where the microprocessor operates under the control of a program stored in the memory.

Abstract: The present invention relates to a process for the preparation of an oxazoline compound which is easily chemically converted to a beta-amino-alpha-hydroxy acid or a gamma-amino-beta-hydroxy acid. The method comprises producing a compound of the following formula (4) using .alpha.-amino acid. The produced compound (4) is subjected to an intramolecular cyclization to produce an oxazoline compound of the following formula (3). The oxazoline compound (3) is oxidized at a vinyl group with RuCl.sub.3 or NaIO.sub.4 to produce an oxazoline compound of the following formula (1) which is easily chemically converted to a beta-amino-alpha-hydroxy acid. Alternatively, the oxazoline compound (3) may also be treated with 9-borabiclo[3.3.1]nonane such that a hydroxy group is introduced into the end of the vinyl group of the oxazoline compound(3). The introduced end hydroxy group is oxidized with RuCl.sub.3 or NaIO.sub.

Abstract: A method for forming the cylindrical lower electrode of a capacitor includes the steps of providing a semiconductor substrate, and then forming an insulation layer over the substrate. Next, a contact opening is formed in the insulation layer, and then a conductive layer is formed, filling the contact opening and covering the insulation layer. Subsequently, a patterned photoresist layer is formed over the conductive layer. Thereafter, silylated photoresist spacers are formed on the sidewalls of the photoresist layer. Finally, using the spacers as a mask, the photoresist layer and a portion of the conductive layer are etched away to form the cylindrical-shaped lower electrode of a capacitor.

Abstract: A method for forming a hemispherical silicon grain (HSG) layer on a polysilicon electrode is provided. The method is suitable for a substrate, which has a dielectric layer over the substrate with an opening to expose the substrate, and a polysilicon layer is formed over the substrate. A portion of the polysilicon layer is removed above dielectric layer other than the opening region. Each sidewall of the polysilicon layer is slanted so that a trapezoidal polysilicon base is formed. A buffer layer is formed over the trapezoidal polysilicon base. An ion implantation process is performed to form an amorphous silicon layer with sufficient depth on a top surface region of the trapezoidal polysilicon base. The buffer layer includes silicon oxide or silicon nitride. During ion implantation, oxygen or nitrogen elements can also be bombarded into the amorphous silicon layer so as to buffer the amorphous silicon layer to be re-crystallized. A selective HSG layer is formed on the trapezoidal polysilicon electrode base.

Abstract: A method of manufacturing MOS device including the steps of providing a semiconductor substrate that has a device isolation structure thereon, and then depositing a gate oxide layer, a polysilicon layer and an anti-reflection coating in sequence over the substrate. Next, a gate structure is patterned out of the gate oxide layer, the polysilicon layer and the anti-reflection coating. Then, spacers are formed on the sidewalls of the gate structure. Thereafter, a metal silicide layer is formed over source/drain regions. After that, an inter-layer dielectric (ILD) layer is formed over the gate structure and the entire substrate. Then, the inter-layer dielectric layer is planarized to expose the anti-reflection coating. Next, the anti-reflection coating is removed, and then a barrier layer is deposited over the inter-layer dielectric layer and the polysilicon layer. Subsequently, a conductive layer is deposited over the barrier layer.

Abstract: A CMOS sensor structure and method of manufacture that includes the fabrication of a special shallow trench isolation structure. Besides isolating the active region for forming the CMOS sensor device, the shallow trench isolation structure has a special reflective plug embedded inside capable of reflecting incoming light onto the sensitive region of the CMOS sensor. Hence, the interactive length of incoming light with the light sensitive region can be increased, thereby increasing the contrast ratio and light sensitivity of the CMOS sensor.

Abstract: A method for fabricating an improved structure of a high-bias device includes forming multiple doped wells between source/drain regions and a P-type substrate. The doped wells have an increasing order of dopant density from the P-type substrate for the P-type dopant or from a first N-type well for an N-type dopant. The doped multiple wells enclose the source/drain regions so that the source/drain regions do not directly contact with the substrate.

Abstract: An alignment and exposure process that use the same incident beam. A substrate having a photoresist formed on an upper surface of the substrate is provided. At least one alignment mark is located on a bottom surface of the substrate. A mask is located over the photoresist. An incident beam is projected onto a light splitter over the mask, wherein the incident beam is reflected onto the alignment mark to align the mask with the substrate. The first light is split into a transmission light and a reflection light. The transmission light passes through the light splitter and the mask to expose the photoresist and the reflection light is projected onto the alignment mark to dynamically align the mask with the substrate.

Abstract: A seating device including a frame, a seat fitted above the frame and surrounded by a seat shell and coverable by an upper half-shell. The upper half-shell is hinged to the seat shell and in covering relationship to the seat. The seat shell and the half-shell together form a ball and the half-shell further takes the form of a back rest.