Patents Represented by Attorney Hinman, Howard & Kattell, LLP
  • Patent number: 7013563
    Abstract: A method for testing opening patterns in an active area of a PCB wherein two arrays of test patterns of apertured pads are analyzed following drilling therethrough in accordance with a specified manner. Specifically, the outer patterns are first tested and if failure results in one or more of said patterns, an inner array of patterns closer to the active area are then tested and, significantly, only the respective test pattern nearest the associated array of openings is used to determine whether said array of openings meets the designated spacing criteria.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: March 21, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventor: John Durkot
  • Patent number: 6995322
    Abstract: A circuitized substrate including a plurality of conductive and dielectric layers and also a plurality of conductive thru-holes therein for passing high speed signals, e.g., from one component to another mounted on the substrate. The substrate utilizes a signal routing pattern which uses the maximum length of each of the thru-holes wherever possible to thereby substantially eliminate signal loss (noise) due to thru-hole “stub” resonance. A multilayered circuitized substrate assembly using more than one circuitized substrate, an electrical assembly using a circuitized substrate and one or more electrical components, a method of making the circuitized substrate and an information handling system incorporating one or more circuitized substrate assemblies and attached components are also provided.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: February 7, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Benson Chan, John M. Lauffer
  • Patent number: 6964884
    Abstract: A circuitized substrate in which three conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to two dielectric layers. Each of the foil surfaces which physically bond to a respective dielectric layer are smooth (e.g., preferably by chemical processing) and may include a thin, organic layer thereon. One of the conductive layers may function as a ground or voltage (power) plane while the other two may function as signal planes with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: November 15, 2005
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Benson Chan, John M. Lauffer
  • Patent number: 6958106
    Abstract: A method of removing selected portions of material from a base material using a plurality of different depth cuts (e.g., using laser cutting) such that apertured sections (or segments) are expeditiously removed for eventual use with another component or otherwise. In one example, the segmented section so removed can be used to bond various elements of an electronic package which in turn can then be positioned and used within an information handling system such as a computer, server, mainframe, etc.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: October 25, 2005
    Assignee: Endicott International Technologies, Inc.
    Inventors: Timothy E. Antesberger, John S. Kresge
  • Patent number: 6905589
    Abstract: A method of making a circuitized substrate in which a commoning layer is used to form multiple, substantially vertically aligned conductive openings in a multilayered component such as a laminate interposer for coupling a chip to a printed circuit board or the like. The structure, including such a chip and circuit board is ideally suited for use within an information handling system.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: June 14, 2005
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Frank D. Egitto, Voya P. Markovich, Thomas R. Miller
  • Patent number: 6815837
    Abstract: An electronic package and information handling system utilizing same wherein the package substrate includes an internally conductive layer coupled to an external pad and of a size sufficiently large enough to substantially prevent cracking, separation, etc. of the pad when the pad is subjected to a tensile pressure of about 1.4 grams per square mil or greater.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: November 9, 2004
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventor: David Alcoe