Abstract: Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type.
Type:
Grant
Filed:
November 30, 2005
Date of Patent:
January 12, 2010
Assignee:
Fairchild Korea Semiconductor, Ltd.
Inventors:
Chong-man Yun, Kwang-hoon Oh, Kyu-hyun Lee, Young-chull Kim
Abstract: A chromatography and fluidic device with connections capable of automated component changing, diagnostic leak and current sensing. The chromatography-electrospray device contains a chromatography column, a pre-column, a spray emitter, or other fluidic component imbedded within one or more inserts. The inserts are robotically placed in receiving hardware, and a “plug and play” compression fitting connection mechanism makes the fluidic seals in an automated fashion. A plurality of sensors capable of detecting leaks is situated in the device near leak-prone regions. The electrospray emitter has a current sensing electrode in proximity of the electrospray region, capable of detecting the electrospray current. In conjunction with an electronics system, these sensors allow for system and component diagnostics. The diagnostic information may then be used for manual or automated system repair.
Abstract: Floor surface scrubbing and resurfacing equipment including a hydraulic system and adjustable linkages to allow a user to adjust particular features to suit the equipment for different applications.
Abstract: The invention provides a flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a taped leadframe with a plurality of leads and a non-conducting tape placed thereon. The electrical paths are printed on the tape to connect the features of the semiconductor device to the leads and an encapsulation layer protects the package. In a second embodiment, the MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package according to each embodiment.
Type:
Grant
Filed:
February 28, 2006
Date of Patent:
December 29, 2009
Assignee:
Fairchild Semiconductor Corporation
Inventors:
Seung-Yong Choi, Ti Ching Shian, Maria Cristina B. Estacio
Abstract: Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the, same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.
Type:
Grant
Filed:
November 6, 2006
Date of Patent:
December 29, 2009
Assignee:
Fairchild Semiconductor Corporation
Inventors:
Martin E. Kordesch, Howard D. Bartlow, Richard L. Woodin
Abstract: Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.
Abstract: A method is disclosed for motivating a user of a spirometry system 20 having a display screen 12, an air-tube 22, a flow measurement sensor 24 operatively associated with the air-tube 22, a display screen 26, and an associated processor 30. A motivational animation is displayed on the display screen 12 having a first aspect that reflects a relative evaluation of a determined peak flow rate to a goal value therefor and having a second aspect that reflects a relative evaluation of a determined total flow volume to a goal value therefor. The processor 30 repeatedly updates the motivational animation during the period of use of the spirometer to reflect the degree of achievement of both of the goal values by the user.
Abstract: An electrical fuse has a region of a first conductivity type in a continuous type polysilicon of a second conductivity type that is opposite the first conductivity type. In one embodiment of the invention the PN junction between the region and the poly fuse is reverse biased.
Abstract: Disclosed in this specification is a luminaire with a vented iris controller disposed on the external surface of the housing of the luminaire. The controller is for dilating and constricting the iris, thus controlling the size of the illuminated spot, wherein the iris controller is comprised of a hollow cylinder, rotatable relative to the housing. The cylinder has an inner ring and an outer ring, wherein the inner ring and outer ring are connected by a plurality of braces and vented spaces are present between each of the braces. Advantageously, the vented spaces help keep the outer ring cool, thus facilitating the operation of the iris controller by a user.
Type:
Grant
Filed:
March 27, 2007
Date of Patent:
November 17, 2009
Assignee:
Welch Allyn, Inc.
Inventors:
Richard A. Tamburrino, Roger W. Leseberg, Michael T. McMahon, Ervin Goldfain
Abstract: A medical device, such as an electrocardiogram (ECG) monitoring apparatus, provides galvanic isolation between low voltage electronics and a plurality of externally exposed ECG (patient contact) lead wires and electrodes. The ECG lead wires and/or electrodes can potentially make unwanted contact with sources of high voltage, such as from defibrillation pulses generated by defibrillation devices. The defibrillation pulses can cause damage to the low voltage electronics within the ECG monitoring apparatus. Electrical resistance is provided outside of the ECG lead wires and electrodes and separate from the low voltage electronics to protect against misdirection of a defibrillation pulse towards the low voltage electronics, and to protect against misdirection of a defibrillation pulse away from the patient for which the benefit of the defibrillation pulse is intended.
Type:
Grant
Filed:
September 29, 2005
Date of Patent:
November 17, 2009
Assignee:
Welch Allyn, Inc.
Inventors:
Michael D. McAtamney, Jim J. Shortt, Rudolf P. Ruizenaar, John P. Kroetz, Daniel R. Sommers, John A. Melquist, Alexius O. Looije
Abstract: A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact 27 is thicker than 250 Angstroms and may be between 2000 and 4000 Angstroms. A termination structure is provided by ion milling an annular region around the Schottky contact.
Type:
Grant
Filed:
April 21, 2008
Date of Patent:
November 17, 2009
Assignee:
Fairchild Semiconductor Corporation
Inventors:
William F. Seng, Richard L. Woodin, Carl Anthony Witt
Abstract: A semiconductor integrated circuit including an LDMOS device structure comprises a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer. First and second spaced-apart source regions of a first conductivity type are formed in a portion of the layer between the pair of gate structures with a first region of a second conductivity type formed there between. A lightly doped body region of a second conductivity type is formed in the semiconductor layer, extending from below the source regions to below the gate structures and extending a variable depth into the semiconductor layer. This body region is characterized by an inflection in depth in that portion of the body region extending below the first region.
Abstract: An improved electrical plug-and-socket connectors with screw-type clamping connections has a step-shaped screw brake for protecting against loss of the clamping screw of connecting stranded conductors of electrical components having as the clamping mode a screw-type clamping connection. The screw brake has one, two or more strips. The plug-and-socket connector has a screw-type connection, having an insulating part, arranged to accommodate at least one contact insert. The contact insert has a substantially cylindrical shape and comprises a contact portion for electrical/mechanical connection to an oppositely shaped contact piece of a matched plug-and-socket connector at a first end of the contact insert. It further comprises an insertion opening for at least one connecting stranded conductor at a second end of the contact insert, there opening in the insertion opening a screw hole which is oriented substantially transversely relative to the central longitudinal axis thereof and comprises an internal thread.
Abstract: A wide bandgap device in parallel with a device having a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device.
Type:
Grant
Filed:
July 25, 2007
Date of Patent:
September 8, 2009
Assignee:
Fairchild Semiconductor Corporation
Inventors:
Joseph A. Yedinak, Richard L. Woodin, Christopher Lawrence Rexer, Praveen Muraleedharan Shenoy, Kwanghoon Oh, Chongman Yun
Abstract: Disclosed in this specification is a wireless semiconductor package with multiple dies, at least two of which are attached to a thermally and electrically conductive heat sink. The package provides an efficient means for dissipating heat.
Type:
Grant
Filed:
October 9, 2007
Date of Patent:
September 8, 2009
Assignee:
Fairchild Semiconductor Corporation
Inventors:
Paul Armand Calo, Margie T. Rios, Tiburcio A. Maldo, JoonSeo Son, Erwin Ian V. Almagro