Abstract: A cover for the motor housing of a ceiling fan includes a flexible wrap for covering the motor housing and a magnetic assemblage for attaching the wrap to the motor housing. The cover can be insulating, have an outer decorative surface for aesthetic effects, or both. A ship lap joint may be included to secure the ends of the cover together.

Abstract: A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate; a source region and a drain region provided in the substrate; wherein the source region and the drain region are laterally spaced from each other; and a drift region in the substrate between the source region and the drain region. The drift region includes a structure having at least two spaced trench capacitors extending between the source region and the drain region; and further includes a stack having at least a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the first conductivity type, wherein the stack extends between the source region and the drain region and between the at least first and second trench capacitors and in electrical connection to the first and second trench capacitors.

Abstract: A self-locking threaded connection including an externally threaded male part having a hollow center and a series of cooperating members; and an internally threaded female part having a series of cooperating members; the cooperating members consisting of projections and detents. As the parts are threaded together, the reception of the projections into the detents produces both audio and tactile responses indicating that the connection is made and near a destructive over tightening.

Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.

Abstract: A system for limiting the exchange of shock and vibration motions and forces between a load and its supporting structure including an isolator. In one aspect, the isolator is designed for in-line mounting with a support strut. The isolator includes an elastomer member that may be substantially permanently maintained in a compression/shear state.

Abstract: A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.

Abstract: The cargo rack assembly a support rack such as the roof rack of a vehicle to assist in the loading and unloading of cargo onto the support rack. The assembly includes load bars connected to base bars via a pivoting lever; the load bars include straps and load arms for securing cargo to the assembly. The base bars are affixed to the support rack and the load bars and pivoting levers transition between a secured position and a loading/unloading position in a smooth motion. The assembly may include a tensioning system for biasing the load bars to the secure position to aid the user in lifting the cargo.

Abstract: Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters.

Abstract: An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached respectively to the first and second pads, wherein the source of the second transistor is electrically connected to the one or more common source-drain leads. A first clip is attached to the drain of the first transistor and electrically connected to the one or more common source-drain leads. A second clip is attached to the drain of the second transistor and electrically connected to the one or more drain leads located on the outside of the second pad. Molding material encapsulates the lead frame, the transistors, and the clips to form the module.

Abstract: A housing for a portable computing device. An upper surface of the housing facilitates access to at least one interface component. A lower surface of the housing defines a cavity to receive a battery pack. A battery pack, adapted to fit within the cavity, defines at least a portion of a first ridge for receiving an operator's finger, the first ridge having a generally curved configuration enabling said housing to be comfortably held in an operator's hand when the operator's hand is in its naturally relaxed position.

Abstract: Aberrations in an optical system can be detected and measured using a method comprised of a test target in the object plane of a projection system and imaging onto the image plane with the system. The test target comprises at least one open figure which comprises a multiple component array of phase zones, where the multiple zones are arranged within the open figure so that their response to lens aberration is interrelated and the zones respond uniquely to specific aberrations depending on their location within the figure. This is a unique and new method of detecting a variety of aberration types including coma, spherical, astigmatism, and three-point through the imaging onto photosensitive material or image detector placed in the image plane of the system and the evaluation of these images.

Abstract: An electrostatic discharge (ESD) protection network for power MOSFETs includes parallel branches, containing polysilicon zener diodes and resistors, used for protecting the gate from rupture caused by high voltages caused by ESD. The branches may have the same or independent paths for voltage to travel across from the gate region into the semiconductor substrate. Specifically, the secondary branch has a higher breakdown voltage than the primary branch so that the voltage is shared across the two branches of the protection network. The ESD protection network of the device provides a more effective design without increasing the space used on the die. The ESD protection network can also be used with other active and passive devices such as thyristors, insulated-gate bipolar transistors, and bipolar junction transistors.

Abstract: An array of power transistors on a semiconductor chip has serpentine gates separated by alternating source and drain regions. The gates combine rounded ends and rectangular sections joining the rounded ends. This geometry allows the metallization, in which the upper and lower metal layers are substantially congruent with each other, to have a design width that can be increased or decreased with the changes in width matched by the length of the rectangular sections thus allowing flexibility in the design of the power transistors.

Abstract: An electrical fuse has a region of a first conductivity type in a continuous type polysilicon of a second conductivity type that is opposite the first conductivity type. In one embodiment of the invention the PN junction between the region and the poly fuse is reverse biased.

Abstract: A multichip module buck converter 10 has a high side power mosfet 12, a low side power mosfet 22 and a pre-molded leadframe 40 between the two mosfets for connecting the source of mosfet 12 to the drain of mosfet 22. Clips 14, 16, 18 and 26 carry the source, gate and drain terminals of the mosfet from planes parallel but spaced apart to a common plane.

Abstract: The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage.

Abstract: A method of operating a bar code scanning system adapted for assembling information bearing indicia (IBI) information from partial scans of IBI data which may comprise some undecodable characters, the method comprising the steps of: converting light reflected from a target into output signals representative thereof utilizing an image sensor; illuminating the target utilizing an illumination source; directing light from the target to the image sensor array utilizing receive optics; determining if information contained in IBI within the target derived from the output signals is not decodable; transmitting an image of the IBI to a host processor if the IBI is not decoded; and housing the processor, image sensor, receive optics, illumination source and display in a common housing for hand held operation.

Abstract: The present invention relates to a flexible multi-functional logic circuit which switches a current direction to a serial or parallel direction using at least two single electron transistors (SETs) having the same pattern and as many field effect transistors (FETs) as the number of the single electron transistors and performs operations on multi-valued signals using Coulomb oscillation that is the unique characteristic of SET to enable conversion of a single logic circuit to four basic logic circuits of NAND, OR, NOR and AND gates and a device using the same.