Abstract: A smoking device having a self-contained ignition mechanism. The device is in the form of a smoking pipe having a stem and a bowl, a mouthpiece extends through the stem and is connected below the bottom of the bowl; contained substantially within the stem is an igniter and a fuel tank for generating a flame in response to an actuator located on the side of the stem. The igniter generates a torch-like flame which extends into the combustion chamber at a point above the mouth piece pipe at ignite combustible material placed in the bowl.

Abstract: The method of fabricating free standing objects using thermal spraying, preferably of a metal, in the following process. A wire mesh is formed into a three dimensional shape of the desired finished product and the shaped mesh is then thermally sprayed with a coating material to substantially cover the visible portions of the mesh. The preferred coating material is metal.

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure including a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

Abstract: The present invention is intended for use on BiCMOS technology where the BJTs are formed after the FETs. A thin FET protection layer 26 is deposited on the raised and recessed regions 28 of the semiconductor substrate 10. A selectively removable filler layer 30 is then deposited on the FET protection layer 26 with a thickness to over-fill the recessed regions 28 of the gates 24 of the FETs. The selectively removable filler layer 30 is then planarized until the FET protection layer 26 on top of the gates 24 is exposed. The recessed regions 28 between the gates 24 are left substantially filled with selectively removable filler layer 30. The selectively removable filler layer 30 in the region where the BJT is formed is patterned and an opening 32 is made to allow for the depositing of layers of different materials 34, 36, 38, 40, 42, 44 used in the construction of the BJT. The layer of different materials 34, 36, 38, 40, 42, 44 are processed by methods known in the art to form polysilicon emitter 46 of the BJT.

Abstract: A method to planarize a semiconductor surface using a Fence Creation and Elimination (FCE) process is described. Shallow recesses on a semiconductor surface are filled with a filling material. The filling material is deposited on the semiconductor surface to a thickness approximately equal to the depth of the shallow recesses. A selectively etchable material is formed on the filling material. A reverse mask (RM) is used to pattern the selectively etchable material to form segments of the selectively etchable material equal to the pattern of the shallow recesses and aligned to the shallow recesses. Exposed filling material is removed followed by the removal of the segments of the selectively etchable material. The remaining filling material in the shallow recesses forms fences which extend above the surface of the semiconductor. The fences are removed resulting in a planar semiconductor surface.

Abstract: A method of preparing an x-ray mask comprising providing a substrate, and applying sequentially to a surface of the substrate i) an etch stop layer resistant to etchant for an x-ray absorber, and ii) an x-ray absorber layer. The method then includes removing a portion of the substrate below the layers to create an active region of the substrate above the removed portion of the substrate and an inactive region over remaining portions of the substrate, applying a resist layer above the absorber layer, and exposing a portion of the resist layer using electron beam irradiation and developing the resist layer to form a latent mask image over the active region of the substrate.

Abstract: The present invention provides a method of forming a capacitor in a last metal wiring layer, and the structure so formed.

Abstract: A method of reducing the planarization defects produced during the manufacture of semiconductor devices. A sacrificial layer, having defects produced during a interconnection feature planarization step, is removed prior to the formation of subsequent layers to reduce the replication of unwanted defects.

Abstract: A method for removing contaminants from a substrate surface having a pattern formed on the surface. The method involves rinsing the substrate and pattern with water to remove acid reactive material. The substrate and pattern are then washed with an acid whose concentration is too low to attack the material that forms the pattern. Then the substrate is washed with water to remove the acid.

Abstract: A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.

Abstract: A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.

Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially- similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.

Abstract: A method for controlling the composition of a chemical bath in which predictive dosing is used to account for changes in the composition of the bath in which the operating characteristics of the process are partitioned into a plurality of operating modes and the consumption or generation of materials related to the process are determined empirically and additions of material are made as appropriate.

Abstract: A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable.

Abstract: A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low k nanopore/nanofoam dielectric material adjacent the conductive line ends.

Abstract: A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The process may be accomplished by providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer.

Abstract: The present invention provides a method of preventing the build-up of polishing material within low areas of a substrate during polishing. Following the blanket deposition of a first layer, a selectively removable material is deposited over the first layer, wherein the selectively removable material fills the low areas. A surface of the substrate is polished removing the excess first layer and selectively removable material from the surface, leaving the first layer and selectively removable material within the low area. Following polishing, the selectively removable material is removed from the low areas prior to the deposition of a second layer.

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

Abstract: A method of measuring a width of an undoped or lightly doped polysilicon line is disclosed. The width measuring method includes generating carriers in the polysilicon line with an energy source; measuring a capacitance between the polysilicon line and a substrate separated from the polysilicon line by a dielectric layer; and determining a line width of said polysilicon line from the measured capacitance. The capacitance measurement includes connecting first and second probes to the polysilicon line; connecting a third probe to the substrate; connecting a first terminal of a capacitance meter to the first and second probes; connecting a second terminal of the capacitance meter to the third probe; and applying a direct current bias across the first and second probes. A capacitor may be connected between the first and second probes. Further steps include, connecting a fourth probe to a conductor that supports the substrate; and connecting the fourth probe to the third probe.