Abstract: A polishing apparatus for polishing a substrate. The polishing apparatus has a slurry delivery system for delivering slurry to the apparatus; a porous polishing pad having an upper surface at which the substrate is polished; and a rotating platen upon which the porous pad lies. The rotating platen has a recess which has a first portion in communication with the delivery means for delivering slurry into the first portion. The recess further has a second portion extending under the polishing pad. Slurry is delivered from the first portion to the second portion and to the upper surface of the pad where it aids in the polishing of the substrate. Preferably, the first portion of the recess is situated such that the slurry delivered to the top surface returns to the first portion for removal or reuse due to the rotational force of the rotating platen.

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of a chip at increased frequencies.

Abstract: A multilayer interconnected electronic component having increased electromigration lifetime is provided. The interconnections are in the form of studs and comprise vertical side walls having a refractory metal diffusion barrier liner along the sidewalls. The stud does not have a barrier layer at the base thereof and the base of the stud contacts the metallization on the dielectric layer of the component. An adhesion layer can be provided between the base of the stud and the surface of the metallization and the adhesion layer may be continuous or discontinuous. The adhesion layer is preferably a metal such as aluminum which dissolves in the stud or metallization upon heating of the component during fabrication or otherwise during use of the component. A preferred component utilizes a dual Damascene structure.

Abstract: Methods for forming metal interconnects are provided. An insulating layer is formed on top of a substrate and a via is formed in the insulating layer reaching to the substrate. The via then is filled with a sacrificial material and a trench aligned over the via is formed by removing an upper portion of the insulating layer and an upper portion of the sacrificial material within the trench. The sacrificial material preferably is selected to etch faster than the insulating layer. After forming the trench, remaining sacrificial material in the via is removed and the via and the trench are filled with a conductive material. In addition to a single insulating layer, the insulating layer on top of the substrate may comprise a first insulating layer formed on top of the substrate, an etch stop layer formed on top of the first insulating layer and a second insulating layer formed on top of the etch stop layer.

Abstract: A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETS; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device's channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer.

Abstract: The advantages of the invention are realized by a chip-on-chip module having at least two fully functional chips, electrically connected together, and a chip-on-chip component connection/interconnection for electrically connecting the fully functional chips to external circuitry.

Abstract: A ferric nitrate-alumina based slurry useful for Chemical-Mechanical-Polishing of tungsten metallurgy and silica based oxides on semiconductor substrates in which the suspension and stability of abrasive material in the slurry is essentially stable. The slurry formulation is balanced to provide low residue of foreign material after polishing and due to its reduced ferric nitrate concentration will be less corrosive than prior art slurries. The recipe for the slurry includes of a 30% wt silica suspension, about 800 ml of 40% by wt ferric nonahydrate and enough 70% wt nitric acid to adjust the pH of the slurry to about 1.2 to 1.4.

Abstract: A method and apparatus for reducing the risk of environmental contamination from mercury spillage during carry over between processing tanks during the gold ball bond removal process by providing a self-contained, compact, environmentally safe system for use with toxic chemicals and liquids. The present invention provides a self-contained, integrally molded enclosure upper and lower chambers separated by a partition. The partition has a plurality of stations integrally formed therein, each of which is capable of containing a chemical liquid. The method comprises dipping a slide containing the semiconductor chip first into a toxic liquid, then into a first decontamination station and finally into a second decontamination station.

Abstract: A method and apparatus are provided for the electroplating on only one side of a substrate immersed in an electroplating bath using a device which holds the substrate to be plated in spaced relation to an inhibitor electrode of the device. To fabricate x-ray masks, a boron doped silicon substrate is secured to a dielectric clamp ring which clamp ring has a through opening which overlies the inhibitor electrode. A cathode structure overlies the clamp ring and the cathode structure, substrate and clamp ring are secured to the device by a pivotable, locking mechanism. A space is formed between the back side of the substrate and the surface of the inhibitor electrode so plating occurs on the surface of the inhibitor electrode. The substrate holding apparatus comprises a plate member to which the inhibitor electrode is secured. The clamp holding the substrate overlies the inhibitor electrode and a cathode structure is secured against the plate member.

Abstract: A photolithographic mask comprises a first plurality of image segments etched into a mask substrate to a first level imparting a predetermined phase shift with respect to electromagnetic radiation of a predetermined frequency, preferably a 90° phase shift, and a second plurality of image segments etched into the mask substrate to a second level imparting a phase shift of 180° more or less than the phase shift of the first plurality of image segments with respect to the predetermined electromagnetic radiation, preferably a 270° phase shift. The first and second segments are disposed adjacent each other on a substrate and positioned such that an intersection of the predetermined electromagnetic radiation passing through the segments causes printable images to be created below the substrate when exposed to the predetermined electromagnetic radiation.

Abstract: A method for developing copolymer photosensitive resists wherein a single solvent is used in conjunction with a puddle develop tool. The copolymer resist is ZEP 7000 and the developer is ethyl 3-ethoxy propionate (EEP).

Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to at least a thickness equal to a predetermined height so as to provide raised and lowered regions of the filler material. The raised regions of the filler material may then be selectively removed without removing the filler material in the lowered regions.

Abstract: A method of producing an asymmetrical semiconductor device with ion implantation techniques and semiconductor devices constructed according to this method in which a barrier of ion absorbing material of height h is positioned beside a structure on a semiconductor surface. The barrier is located at a maximum distance d from one side of the structure, and an angled ion implant is directed at the side of the structure. The maximum distance d of the barrier from the side of the structure is equal to the height of the barrier h divided by the tangent of the angle of the ion implant so that the side of the structure is shadowed from the ion implant. A second ion implant is directed to the opposite side of the structure on the semiconductor surface, thereby forming a desired implant and producing the asymmetrical semiconductor device.

Abstract: An apparatus for and method of detecting the presence of a brush used in a semiconductor wafer cleaner for post-CMP processing is described. Semiconductor wafers are loaded into the wet environment of the wafer cleaner, affixed to a rotatable fixture and rotated at high speed. The rotatable fixture is effectuated by a servo motor linked to a servo controller and a torque monitor. A first torque on the rotating wafer is calculated prior to the start of the brush cleaning cycle. During the brush cleaning cycle, as the brush within the brush cleaner contacts the rotating wafer, the torque on the wafer increases and a second torque is calculated. If, during the brush cleaning cycle, the second torque calculation is substantially equal to the first torque calculation, the brush cleaner is not contacting the wafer and cleaning has not progressed. A tool user can be notified to reaffix the brush within the cleaner.

Abstract: Mask programmable conductors of the same construction as the mask layers they define are utilized for mask vintage identification. When the actual mask layer is altered, the change is recorded within the mask itself. Mask identification can be fabricated to identify the following type of mask layers: DT—deep trench; SS—surface strap; DIFF—Diffusion; NDIFF—N Diffusion; PDIFF—P Diffusion; WL—N wells; PC—polysilicon gates; BN—N diffusion Implant; BP—P diffusion Implant; C1—first contact; M1—first metal layer; C2—second contact; and, M2—second metal layer. Conducting paths that incorporate, in series, the mask programmable conductor technology devices are: M1-C1-PC-C1-DIFF-C1-M1-C2-M2; M1-C1-PDIFF-SS-DT-SS-PDIFF-C1-M1-C2-M2; M2-C2-M1-C1-PC-C1-M1; M2-C2-M1-C1-NDIFF-WL-NDIFF-C1-M1; and, M2-C2-M1-C1-NDIFF-C1-M1-C1-PC-C1-M1. These conducting paths are electrically opened with the omission of any of the layers in the series path.

Abstract: A process for forming capacitors in a semiconductor device.

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure comprising a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

Abstract: A method and apparatus for repairing transparent defects in a transfer layer circuit pattern in the process of fabricating an attenuated mask is provided comprising forming a sacrificial removable layer on the transfer layer including the part of the transfer layer having a transparent defect and then forming a patch to cover the transparent defect. After applying the sacrificial removable layer and patch, the sacrificial removable layer and unwanted exposed attenuated mask material is removed leaving the patch having an undercoating of sacrificial removable layer in the transparent defect region. The undercoat sacrificial removable layer is then at least partially etched and the patch and sacrificial layer removed by a lift off procedure. The transfer layer is then removed leaving the attenuated mask having the desired circuit pattern on the surface of the transparent mask substrate. Attenuated masks made using the method and apparatus of the invention are also provided.

Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.

Abstract: A capacitor structure formed on a semiconductor substrate may include a first interconnect wiring (such as copper damascene) and a first conductive barrier layer in contact with the first interconnect wiring. A first capacitor plate, a capacitor dielectric structure and a second capacitor plate may also be included over the first conductive barrier layer. A second conductive barrier layer may be formed on the second capacitor plate and a second planar insulating structure may be formed over the second capacitor plate. Finally, a second interconnect wiring may be embedded within a second planar insulator structure.