Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.

Abstract: A voltage generator for an integrated circuit chip comprises an integrated circuit chip with a power supply having a voltage available to the chip; an inductor on or in contact with the integrated circuit chip electrically connected to the power supply through which current is driven; and a clock adapted to interrupting current flowing from the power supply through the inductor at desired time intervals to create voltage spikes above the power supply voltage. The inductor may comprise a portion of the lead frame connecting the integrated circuit chip to an integrated chip package. The voltage spikes generate a voltage about two or more times the voltage of the power supply available to the chip. Where the integrated circuit chip includes an electrical fuse and/or a battery, the fuse on the chip may be adapted to be programmed or the battery charged by the voltage spikes.

Abstract: Integrated circuits are provided which permit backside probing while being operated. Conductive trenches are fabricated into the surface of semiconductor chip at preselected locations. Access to specific electrically connected nodes of the integrated circuit can be effected through the conductive trenches by backside thinning and milling of the semiconductor chip followed by e-beam probe or mechanical probe usage.

Abstract: A method and structure for the invention includes an integrated memory structure having a built-in test portion. The integrated memory structure has memory cells, bitlines and wordlines connected to the memory cells, wordline decoders connected to a plurality of the wordlines, bitline restore devices connected to the bitlines for charging the bitlines during read and write operations, and a clock circuit connected to the wordlines. During a test mode the wordline decoders simultaneously select multiple wordlines that the bitline restore devices maintain in an active state and the clock circuit maintains th multiple wordlines and the bitline restore devices in an active state for a period in excess of a normal read cycle. The invention also includes transistors which are connected to the memory cells. The transistors include bitline contacts which are stressed during the test mode.

Abstract: A method of forming a damascene structure using a sacrificial conductive layer to provide a uniform focus plane for the photolithography tool during formation of circuit features. In particular, a metal layer is provided between the insulative layer and the photoresist, upon which the capacitive sensors of the photolithography tool focus during the formation of the circuit features, namely, troughs and vias.

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

Abstract: A semiconductor fuse structure having a conductive fuse material abutting a first and second conductive line is provided. The fuse of the present invention does not substantially damage the surrounding semiconductor material therefore it can be used with a wide variety of materials including porous, mechanically fragile, low dielectric constant materials and high conductive metals like Cu. Methods of fabricating such a semiconductor fuse structure are also provided herein.

Abstract: A method is presented for measuring and monitoring the mechanical stress at the device level which occurs intrinsically during the fabrication process or which is induced via extrinsic means. The method applies the fact that the current-voltage (I-V) characteristics of a diode change as the diode is subjected to mechanical stress. The method is applicable to monitoring stress at the microscopic and device levels at various stages in the semiconductor wafer fabrication process. Apparatus for implementing the method is also presented.

Abstract: Interconnections including copper conductor lines, vias and Damascene lines comprise an insulator or dielectric having openings therein, a first adhesion promoting conductive barrier liner material on the walls and base of the opening, a first conductive layer on the first adhesion material layer, the first conductive layer having a predetermined cross-sectional area and having electromigration resistance, a second adhesion promoting/conductive barrier layer on the first conductive layer and a soft low resistant metal such as copper filling the remainder of the opening forming the line or via. These interconnections have enhanced operating and electromigration life particularly if copper is missing or partially missing in the copper interconnections due to the copper deposition process.

Abstract: An apparatus and method of planarizing objects, particularly electronic components. The off-concentric polishing system of the present invention comprises at least two polishing platens positioned adjacent each other such that the polishing portions of the platens are substantially co-planar. At least one wafer carrier is moveably mounted over the at least two platens such that a wafer may be polished by more than one platen substantially simultaneously. The platen configurations may be in a linear or non-linear configuration such that the wafer being polished is no longer centrally disposed over a single platen but is off-concentrically positioned over multiple platens. The off-concentric positioning of the wafer provides enhanced slurry distribution and endpoint detection. The present invention reduces time and cost in manufacturing electronic components by engaging several polishing conditions simultaneously without the need for sequential polishing.

Abstract: A method of fabricating an interconnect for a semiconductor device is disclosed. The method comprises: forming a dielectric layer on a semiconductor substrate; forming a trench in the dielectric layer; placing the semiconductor substrate in a plasma deposition chamber having a tantalum target; initiating a plasma in the presence of nitrogen in the plasma deposition chamber; and depositing an ultra-thin layer comprising tantalum and nitrogen in the trench.

Abstract: An integrated circuit device structure having probe pad extensions in electrical communication with the wire bond pads and a method for performing failure analysis thereon. The invention provides an improved probing system for wire bond packages such that neither the wire nor the wire bond from the pads on the chip surface need be removed during testing procedures. Included in the integrated circuit device is a plurality of conductive pads having a first area for receiving a wire bond and a second area for receiving a probe, wherein the second area abuts, and is an electrical communication with the first area.

Abstract: A method and structure to provide a circuit adapted to sense the status of a fuse includes an imbalanced sense amplifier latch which includes first and second nodes connected to the fuse. The first node is connected to a fuse and is weaker than the second node, allowing the first node to sense a different voltage level. The voltage difference between the nodes indicates the conductive status of the fuse.

Abstract: A printed wiring board structure having peripheral power input. A printed wiring board having internal conductive layers, wherein each internal conductive layer contains a plurality of tabs extending therefrom. Tabs of similar voltage are vertically aligned within the printed wiring board. A frame within which the printed wiring board is mounted is also provided. The frame, having connections mounted within an inner surface of the frame, electrically contacts the tabs along the periphery of the printed wiring board.

Abstract: A method and structure for an integrated circuit technology segment test structure including a plurality of technology test structures connected together as a chain of elements and a plurality of externally probable regions positioned along said chain of elements, said externally probable regions being positioned so as to enable location of a failed test structure.

Abstract: A method and structure is described which improves the manufacturability of integrated circuit interconnect and stud contacts in contact with semiconductor substrates and upper levels of metallization. The monolithic structure is formed from a thick layer of refractory metal. A variation in the monolithic structure is in the use of a dual damascene local interconnect portion of the structure which allows the local interconnect to pass over structures previously formed on the substrate.

Abstract: A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable. The magnetic device can be programmed into one of three magnetic field orentations or states. Conventional VLSI fabrication steps are used for compatability with low-k dielectric Back-End-Of-Line (BEOL) processing.

Abstract: A recessed bond pad within an electronic device on a substrate, and associated method of fabrication. The electronic device includes N contiguous levels of interconnect metallurgy, with level N coupled to the substrate. A first group of metallic etch stops is formed at level M≦N, and a second group of metallic etch stops is formed at level M−1. The second group conductively contacts the first group in an overlapping multilevel matrix pattern. A recessed copper pad is formed at level K≦M−2. A cylindrical space that encloses the metal pad encompasses levels 1,2, . . . , M−1 above the first group, and levels 1,2, . . . , M−2 above the second group. Dielectric material in the cylindrical space is etched away, leaving a void supplanting the etched dielectric material, and leaving exposed surfaces of the cylindrical space. The copper pad is exposed and recessed within the cylindrical space.

Abstract: A method for inspecting a plurality of similar structures in the surface of a workpiece includes providing a workpiece having a plurality of regions, each of the regions including at least two different materials, generating an image from each of the regions such that an image contrast between the two materials is enhanced and classifying the images into at least two classes including an acceptable class of images and unacceptable class of images.

Abstract: A method and rotational mask scanning apparatus for exposing a plurality of images on a workpiece, include a rotatable mask having a pattern of image segments thereon, an optical system for projecting the image segments onto the workpiece, and a device for at least one of rotating the mask and for moving the workpiece so as to continuously expose a plurality of regions on the workpiece with the pattern of image segments.