Abstract: Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed. A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging.

Abstract: A method is provided for making optical waveguide structures in a semiconductor device wherein a rectangular cross-section low index of refraction material is encapsulated in a trench by a high index of refraction material. The waveguide structures may be made in a device containing copper conductors in trenches by forming new trenches to hold the optical waveguide. Copper conductor containing trenches may also be made in an electronic component containing waveguide structures and a further method is provided for forming an optical waveguide structure by replacing a copper containing trench with the waveguide structure in an electronic component having a plurality of copper containing trenches. All the methods use conventional techniques so that the fabrication of a semiconductor device containing both optical waveguide structures and copper conductor structures can be made both efficiently and economically.

Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

Abstract: A technique for post-processing a conventionally completed semiconductor device having a final passivation layer and bond pads exposed through the final passivation layer. The technique includes forming a protective film over the final passivation layer and exposed bond pads of the semiconductor device, and thereafter performing post-processing of the completed semiconductor device. Post-process structures, such as charge-coupled devices, can be formed above the protective film during this post-processing. Subsequent to the post-processing, the protective film is selectively etched to again expose the bond pads.

Abstract: A high laser absorption copper fuse can minimize the laser energy needed to delete the fuse portion of the conductor. Significantly, this type of fuse structure would allow for formation of copper fuses that can be deleted with appreciably less incident energy, mainly by increasing the absorption of the fuse link at the given incident laser energies. A metal wiring line contains a fuse link segment wherein the fuse link segment is composed of a stack of at least two metals. The underlayer material in the stack of metals is the primary electrical copper conductor, and the overlayer metal, also an electrical conductor, primarily tungsten or titanium-tungsten in composition, has predetermined thickness and optical properties chosen such that the combination of the overlayer metal with the underlayer metal provides for high absorption characteristics to incident infrared energy.

Abstract: A tantalum-based liner for copper metallurgy is selectively removed by chemical-mechanical planarization (CMP) in an acidic slurry of an oxidizer such as hydrogen peroxide, deionized water, a corrosion inhibitor such as BTA, and a surfactant such as DUPONOL SP, resulting in a high removal rate of the liner without appreciable removal of the exposed copper and with minimal dishing.

Abstract: An integrated circuit device structure having probe pad extensions in electrical communication with the wire bond pads and a method for performing failure analysis thereon. The invention provides an improved probing system for wire bond packages such that neither the wire nor the wire bond from the pads on the chip surface need be removed during testing procedures. Included in the integrated circuit device is a plurality of conductive pads having a first area for receiving a wire bond and a second area for receiving a probe, wherein the second area abuts, and is an electrical communication with the first area.

Abstract: A method of preparing an x-ray mask comprising providing a substrate, and applying sequentially to a surface of the substrate i) an etch stop layer resistant to etchant for an x-ray absorber, and ii) an x-ray absorber layer. The method then includes removing a portion of the substrate below the layers to create an active region of the substrate above the removed portion of the substrate and an inactive region over remaining portions of the substrate, applying a resist layer above the absorber layer, and exposing a portion of the resist layer using electron beam irradiation and developing the resist layer to form a latent mask image over the active region of the substrate.

Abstract: A recessed bond pad within an electronic device on a substrate, and associated method of fabrication. The electronic device includes N contiguous levels of interconnect metallurgy, with level N coupled to the substrate. A first group of metallic etch stops is formed at level M≦N, and a second group of metallic etch stops is formed at level M−1. The second group conductively contacts the first group in an overlapping multilevel matrix pattern. A recessed copper pad is formed at level K≦M−2. A cylindrical space that encloses the metal pad encompasses levels 1,2, . . . , M−1 above the first group, and levels 1,2, . . . , M−2 above the second group. Dielectric material in the cylindrical space is etched away, leaving a void supplanting the etched dielectric material, and leaving exposed surfaces of the cylindrical space. The copper pad is exposed and recessed within the cylindrical space.

Abstract: A ferric nitrate-alumina based slurry useful for Chemical-Mechanical-Polishing of tungsten metallurgy and silica based oxides on semiconductor substrates in which the suspension and stability of abrasive material in the slurry is essentially stable. The slurry formulation is balanced to provide low residue of foreign material after polishing and due to its reduced ferric nitrate concentration will be less corrosive than prior art slurries. The recipe for the slurry includes of a 30% wt silica suspension, about 800 ml of 40% by wt ferric nonahydrate, liters and enough 70% wt nitric acid to adjust the pH of the slurry to about 1.2 to 1.4.

Abstract: A method of detecting the presence of a brush used in a semiconductor wafer cleaner for post-CMP processing is described. Semiconductor wafers are loaded into the wet environment of the wafer cleaner, affixed to a rotatable fixture and rotated at high speed. The rotatable fixture is effectuated by a servo motor linked to a servo controller and a torque monitor. A first torque on the rotating wafer is calculated prior to the start of the brush cleaning cycle. During the brush cleaning cycle, as the brush within the brush cleaner contacts the rotating wafer, the torque on the wafer increases and a second torque is calculated. If, during the brush cleaning cycle, the second torque calculation is substantially equal to the first torque calculation, the brush cleaner is not contacting the wafer and cleaning has not progressed. A tool user can be notified to reaffix the brush within the cleaner.

Abstract: A method of reworking copper metallurgy on semiconductor devices which includes selective removal of insulator, selective removal of copper, non-selective removal of copper and insulator followed by the redeposition of an insulating copper barrier layer and at least one metallurgical interconnect layer.

Abstract: A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.

Abstract: A method and structure for blowing a fuse including removing an insulator above a fuse link and etching the fuse link.

Abstract: A structure and method for polishing a device include oscillating a carrier over an abrasive surface (the carrier bringing a polished surface of the device into contact with the abrasive surface, the oscillating allowing a portion of the polished surface to periodically oscillate off the abrasive surface), optically determining a reflective measure of a plurality of locations of the polished surface as the portion of the device oscillates off the abrasive surface and calculating depths of the locations of the polished surface based of the reflective measure.

Abstract: A semiconductor wafer rework process sideways etches an underlying layer of metal to remove a difficult to etch upper layer of metal without substantially etching that upper layer and without damaging permanent layers of the wafer. If the underlying layer of metal is TiW and the permanent layer is aluminum, the TiW layer can be sideways etched with a hydrogen peroxide and ammonium hydroxide solution that does not damage aluminum lines that are permanently on the wafer. Thus, difficult to remove intermetallic layers, such as tin-copper or chrome-copper, that are located on an underlying layer of TiW, can be successfully removed without danger of damaging permanent aluminum metallization of the wafer.

Abstract: The present invention relates to a method of integrating a low dielectric material such as DLC into a dual or single damascene wiring structure which contains a dielectric material having a dielectric constant of 4.0 or above. This integration is achieved in the present invention by employing a step of etchingback the high dielectric constant material to expose regions of in-laid wiring present in the single or dual damascene structure. Damascene wiring structures, single or dual, prepared using the method of the present invention are also provided herein.

Abstract: A method and structure for manufacturing Charge-Coupled-Device (CCD) image pick-up devices. The method bonds a first wafer with a second wafer. The first wafer has a CCD layer on a first substrate, wherein the CCD layer includes a plurality of CCD pick-up image arrays. The CCD layer is thin, preferably in a range of 5 to 20 microns, while the substrate is relatively thicker (e.g., 300 microns). The first wafer also includes first conductive pads arranged in a pattern on a surface of the CCD layer such that each CCD array is conductively coupled to a plurality of the first conductive pads. The second wafer has a second substrate that includes a semiconductor material such as silicon, and second conductive pads according to the pattern on a surface of the second substrate. The first wafer is bonded with the second wafer to form a wafer composite, wherein the first conductive pads are joined to the second conductive pads in accordance with the pattern.

Abstract: Non-aqueous cleaning compositions capable of removing cured polyimides and other polymers from a metal circuitry containing substrate such as a semiconductor device for rework and other purposes without any significant adverse affect on the circuitry are provided consisting essentially of alkanolamines, preferably monoethanolamine or monoethanolamine-diethanolamine mixtures and optionally with a solvent such as NMP in an amount less than about 50% by weight. A method is also provided for removing polyimide coatings and other polymers from semiconductor devices using the cleaning compositions of the invention.

Abstract: An electronic switch circuit switches out bad decoupling capacitors on a high speed integrated circuit chip. The circuit comprises a control device that operates in the subthreshold or off device state to detect leakage in a decoupling capacitor. This control device operates in a low impedance state if the capacitor is good and in a high impedance sate if the capacitor is bad. A feedback circuit is connected from an internal node of the capacitor to a gate of the control device so that once a state of the capacitor is detected it can be stored on the gate of the control device. A single external signal source shared by a group of capacitors activates the control device to detect leakage in the capacitor. The circuit operates to switch out capacitors that fail during normal operation.