Patents Represented by Attorney, Agent or Law Firm Howard J. Walter, Jr.
  • Patent number: 7490613
    Abstract: A smoking device having a self-contained ignition mechanism. The device is in the form of a smoking pipe having a stem and a bowl, a mouthpiece extends through the stem and is connected below the bottom of the bowl; contained substantially within the stem is an igniter and a fuel tank for generating a flame in response to an actuator located on the side of the stem. The igniter generates a torch-like flame which extends into the combustion chamber at a point above the mouth piece pipe at ignite combustible material placed in the bowl.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: February 17, 2009
    Inventor: George Iordan
  • Patent number: 6521383
    Abstract: A method of preparing an x-ray mask comprising providing a substrate, and applying sequentially to a surface of the substrate i) an etch stop layer resistant to etchant for an x-ray absorber, and ii) an x-ray absorber layer. The method then includes removing a portion of the substrate below the layers to create an active region of the substrate above the removed portion of the substrate and an inactive region over remaining portions of the substrate, applying a resist layer above the absorber layer, and exposing a portion of the resist layer using electron beam irradiation and developing the resist layer to form a latent mask image over the active region of the substrate.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: February 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Maheswaran Surendra, Douglas E. Benoit, Cameron J. Brooks
  • Patent number: 6503827
    Abstract: A method of reducing the planarization defects produced during the manufacture of semiconductor devices. A sacrificial layer, having defects produced during a interconnection feature planarization step, is removed prior to the formation of subsequent layers to reduce the replication of unwanted defects.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: January 7, 2003
    Assignee: International Business Machines Corporation
    Inventors: Susan G. Bombardier, Paul M. Feeney, Robert M. Geffken, David V. Horak, Matthew J. Rutten
  • Patent number: 6504203
    Abstract: The present invention provides a method of forming a capacitor in a last metal wiring layer, and the structure so formed.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: January 7, 2003
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Stephen E. Luce, Thomas L. McDevitt, Henry W. Trombley
  • Patent number: 6494966
    Abstract: A method for removing contaminants from a substrate surface having a pattern formed on the surface. The method involves rinsing the substrate and pattern with water to remove acid reactive material. The substrate and pattern are then washed with an acid whose concentration is too low to attack the material that forms the pattern. Then the substrate is washed with water to remove the acid.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: December 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Virginia Chi-Chuen Chao, Scott A. Estes, Thomas B. Faure, Thomas M. Wagner
  • Patent number: 6495917
    Abstract: A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: December 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Paul M. Feeney, Robert M. Geffken, Howard S. Landis, Rosemary A. Previti-Kelly, Bette L. Bergman Reuter, Matthew J. Rutten, Anthony K. Stamper, Sally J. Yankee
  • Patent number: 6496053
    Abstract: A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: December 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Timothy Daubenspeck, Kurt R. Kimmel, William A. Klaasen, William T. Motsiff, Rosemary A. Previti-Kelly, W David Pricer, Jed H. Rankin
  • Patent number: 6492207
    Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially- similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: December 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: Dennis P. Bouldin, Timothy H. Daubenspeck, William T. Motsiff
  • Patent number: 6472230
    Abstract: A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: October 29, 2002
    Assignee: International Business Machines Corporation
    Inventors: Kurt R. Kimmel, J. Alex Chediak, William T. Motsiff, Wilbur D. Pricer, Richard Q. Williams
  • Patent number: 6471845
    Abstract: A method for controlling the composition of a chemical bath in which predictive dosing is used to account for changes in the composition of the bath in which the operating characteristics of the process are partitioned into a plurality of operating modes and the consumption or generation of materials related to the process are determined empirically and additions of material are made as appropriate.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: October 29, 2002
    Assignees: International Business Machines Corporation, Novellus Systems, Inc.
    Inventors: John O. Dukovic, William E. Corbin, Jr., Erick G. Walton, Peter S. Locke, Panayotis C. Andricacos, James E. Fluegel, Evan Patton, Jonathan Reid
  • Patent number: 6458630
    Abstract: A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low k nanopore/nanofoam dielectric material adjacent the conductive line ends.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: October 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, William A. Klaasen, William T. Motsiff, Rosemary A. Previti-Kelly, Jed H. Rankin
  • Patent number: 6455914
    Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: September 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Dennis P. Bouldin, Timothy H. Daubenspeck, William T. Motsiff
  • Patent number: 6456082
    Abstract: A method of measuring a width of an undoped or lightly doped polysilicon line is disclosed. The width measuring method includes generating carriers in the polysilicon line with an energy source; measuring a capacitance between the polysilicon line and a substrate separated from the polysilicon line by a dielectric layer; and determining a line width of said polysilicon line from the measured capacitance. The capacitance measurement includes connecting first and second probes to the polysilicon line; connecting a third probe to the substrate; connecting a first terminal of a capacitance meter to the first and second probes; connecting a second terminal of the capacitance meter to the third probe; and applying a direct current bias across the first and second probes. A capacitor may be connected between the first and second probes. Further steps include, connecting a fourth probe to a conductor that supports the substrate; and connecting the fourth probe to the third probe.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: September 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Edward J. Nowak, James C. Li
  • Patent number: 6455778
    Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: September 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Claude Louis Bertin, Thomas George Ference, Wayne John Howell, John Atkinson Fifield
  • Patent number: 6455434
    Abstract: The present invention provides a method of preventing the build-up of polishing material within low areas of a substrate during polishing. Following the blanket deposition of a first layer, a selectively removable material is deposited over the first layer, wherein the selectively removable material fills the low areas. A surface of the substrate is polished removing the excess first layer and selectively removable material from the surface, leaving the first layer and selectively removable material within the low area. Following polishing, the selectively removable material is removed from the low areas prior to the deposition of a second layer.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: September 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Chad R. Binkerd, Jose L. Cruz, Timothy C. Krywanczyk, Brian D. Pfeifer, Rosemary A. Previti-Kelly, Patricia Schink, Amye L. Wells
  • Patent number: 6452209
    Abstract: Integrated circuits are provided which permit backside probing while being operated. Conductive trenches are fabricated into the surface of semiconductor chip at preselected locations. Access to specific electrically connected nodes of the integrated circuit can be effected through the conductive trenches by backside thinning and milling of the semiconductor chip followed by e-beam probe or mechanical probe usage.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: September 17, 2002
    Assignee: International Business Machines Corporation
    Inventor: David P. Vallett
  • Patent number: 6452439
    Abstract: A voltage generator for an integrated circuit chip comprises an integrated circuit chip with a power supply having a voltage available to the chip; an inductor on or in contact with the integrated circuit chip electrically connected to the power supply through which current is driven; and a clock adapted to interrupting current flowing from the power supply through the inductor at desired time intervals to create voltage spikes above the power supply voltage. The inductor may comprise a portion of the lead frame connecting the integrated circuit chip to an integrated chip package. The voltage spikes generate a voltage about two or more times the voltage of the power supply available to the chip. Where the integrated circuit chip includes an electrical fuse and/or a battery, the fuse on the chip may be adapted to be programmed or the battery charged by the voltage spikes.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: September 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: John A. Fifield, Nicholas M. Van heel
  • Patent number: 6449200
    Abstract: A method and structure for the invention includes an integrated memory structure having a built-in test portion. The integrated memory structure has memory cells, bitlines and wordlines connected to the memory cells, wordline decoders connected to a plurality of the wordlines, bitline restore devices connected to the bitlines for charging the bitlines during read and write operations, and a clock circuit connected to the wordlines. During a test mode the wordline decoders simultaneously select multiple wordlines that the bitline restore devices maintain in an active state and the clock circuit maintains th multiple wordlines and the bitline restore devices in an active state for a period in excess of a normal read cycle. The invention also includes transistors which are connected to the memory cells. The transistors include bitline contacts which are stressed during the test mode.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: September 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: Erik A. Nelson, Harold Pilo
  • Patent number: 6444490
    Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: September 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: Claude Louis Bertin, Thomas George Ference, Wayne John Howell, John Atkinson Fifield
  • Patent number: D563064
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: February 26, 2008
    Inventor: Romeo H Vezina