Abstract: A method and apparatus are provided for the electroplating on only one side of a substrate immersed in an electroplating bath using a device which holds the substrate to be plated in spaced relation to an inhibitor electrode of the device. To fabricate x-ray masks, a boron doped silicon substrate is secured to a dielectric clamp ring which clamp ring has a through opening which overlies the inhibitor electrode. A cathode structure overlies the clamp ring and the cathode structure, substrate and clamp ring are secured to the device by a pivotable, locking mechanism. A space is formed between the back side of the substrate and the surface of the inhibitor electrode so plating occurs on the surface of the inhibitor electrode. The substrate holding apparatus comprises a plate member to which the inhibitor electrode is secured. The clamp holding the substrate overlies the inhibitor electrode and a cathode structure is secured against the plate member.

Abstract: A photolithographic mask comprises a first plurality of image segments etched into a mask substrate to a first level imparting a predetermined phase shift with respect to electromagnetic radiation of a predetermined frequency, preferably a 90° phase shift, and a second plurality of image segments etched into the mask substrate to a second level imparting a phase shift of 180° more or less than the phase shift of the first plurality of image segments with respect to the predetermined electromagnetic radiation, preferably a 270° phase shift. The first and second segments are disposed adjacent each other on a substrate and positioned such that an intersection of the predetermined electromagnetic radiation passing through the segments causes printable images to be created below the substrate when exposed to the predetermined electromagnetic radiation.

Abstract: A method for developing copolymer photosensitive resists wherein a single solvent is used in conjunction with a puddle develop tool. The copolymer resist is ZEP 7000 and the developer is ethyl 3-ethoxy propionate (EEP).

Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to at least a thickness equal to a predetermined height so as to provide raised and lowered regions of the filler material. The raised regions of the filler material may then be selectively removed without removing the filler material in the lowered regions.

Abstract: An apparatus for and method of detecting the presence of a brush used in a semiconductor wafer cleaner for post-CMP processing is described. Semiconductor wafers are loaded into the wet environment of the wafer cleaner, affixed to a rotatable fixture and rotated at high speed. The rotatable fixture is effectuated by a servo motor linked to a servo controller and a torque monitor. A first torque on the rotating wafer is calculated prior to the start of the brush cleaning cycle. During the brush cleaning cycle, as the brush within the brush cleaner contacts the rotating wafer, the torque on the wafer increases and a second torque is calculated. If, during the brush cleaning cycle, the second torque calculation is substantially equal to the first torque calculation, the brush cleaner is not contacting the wafer and cleaning has not progressed. A tool user can be notified to reaffix the brush within the cleaner.

Abstract: A method of producing an asymmetrical semiconductor device with ion implantation techniques and semiconductor devices constructed according to this method in which a barrier of ion absorbing material of height h is positioned beside a structure on a semiconductor surface. The barrier is located at a maximum distance d from one side of the structure, and an angled ion implant is directed at the side of the structure. The maximum distance d of the barrier from the side of the structure is equal to the height of the barrier h divided by the tangent of the angle of the ion implant so that the side of the structure is shadowed from the ion implant. A second ion implant is directed to the opposite side of the structure on the semiconductor surface, thereby forming a desired implant and producing the asymmetrical semiconductor device.

Abstract: Mask programmable conductors of the same construction as the mask layers they define are utilized for mask vintage identification. When the actual mask layer is altered, the change is recorded within the mask itself. Mask identification can be fabricated to identify the following type of mask layers: DT—deep trench; SS—surface strap; DIFF—Diffusion; NDIFF—N Diffusion; PDIFF—P Diffusion; WL—N wells; PC—polysilicon gates; BN—N diffusion Implant; BP—P diffusion Implant; C1—first contact; M1—first metal layer; C2—second contact; and, M2—second metal layer. Conducting paths that incorporate, in series, the mask programmable conductor technology devices are: M1-C1-PC-C1-DIFF-C1-M1-C2-M2; M1-C1-PDIFF-SS-DT-SS-PDIFF-C1-M1-C2-M2; M2-C2-M1-C1-PC-C1-M1; M2-C2-M1-C1-NDIFF-WL-NDIFF-C1-M1; and, M2-C2-M1-C1-NDIFF-C1-M1-C1-PC-C1-M1. These conducting paths are electrically opened with the omission of any of the layers in the series path.

Abstract: A process for forming capacitors in a semiconductor device.

Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.

Abstract: A method and apparatus for repairing transparent defects in a transfer layer circuit pattern in the process of fabricating an attenuated mask is provided comprising forming a sacrificial removable layer on the transfer layer including the part of the transfer layer having a transparent defect and then forming a patch to cover the transparent defect. After applying the sacrificial removable layer and patch, the sacrificial removable layer and unwanted exposed attenuated mask material is removed leaving the patch having an undercoating of sacrificial removable layer in the transparent defect region. The undercoat sacrificial removable layer is then at least partially etched and the patch and sacrificial layer removed by a lift off procedure. The transfer layer is then removed leaving the attenuated mask having the desired circuit pattern on the surface of the transparent mask substrate. Attenuated masks made using the method and apparatus of the invention are also provided.

Abstract: A capacitor structure formed on a semiconductor substrate may include a first interconnect wiring (such as copper damascene) and a first conductive barrier layer in contact with the first interconnect wiring. A first capacitor plate, a capacitor dielectric structure and a second capacitor plate may also be included over the first conductive barrier layer. A second conductive barrier layer may be formed on the second capacitor plate and a second planar insulating structure may be formed over the second capacitor plate. Finally, a second interconnect wiring may be embedded within a second planar insulator structure.

Abstract: Eliminating exposure of PN junctions to light capable of invoking a photovoltaic effect and/or inhibiting the oxidation and reduction reactions induced by the photovoltaic effect prevents the electrochemical dissolution of metal components on semiconductor devices by electrolysis. A darkened enclosure for use on tools for wafer CMP, brush cleaning, unloading, and rinsing will eliminate exposure. Alternatively, illumination of a semiconductor wafer can be limited to wavelengths of light that do not provide enough energy to induce a photovoltaic effect. An inhibitor in the CMP slurry and/or post-CMP water rinse blocks the oxidation and/or reduction reactions. A blocking agent, such as a high molecular weight surfactant, will interfere with both the oxidation and reduction reactions at the metal surface. Also, a poisoning agent will impede the reduction portion of electrolysis.

Abstract: A semiconductor fuse structure having a conductive fuse material abutting a first and second conductive line is provided. The fuse of the present invention does not substantially damage the surrounding semiconductor material therefore it can be used with a wide variety of materials including porous, mechanically fragile, low dielectric constant materials and high conductive metals like Cu. Methods of fabricating such a semiconductor fuse structure are also provided herein.

Abstract: Integrated circuits are provided which permit backside probing while being operated. Conductive trenches are fabricated into the surface of semiconductor chip at preselected locations. Access to specific electrically connected nodes of the integrated circuit can be effected through the conductive trenches by backside thinning and milling of the semiconductor chip followed by e-beam probe or mechanical probe usage.

Abstract: An apparatus and method are provided that remove sufficient heat from both SOI and non-SOI semiconductor devices to prevent the devices from overheating during operation. A plurality of thermally conductive pads such as electrically conductive studs are coupled to a first side of a semiconductor device having circuit elements formed thereon. The thermally conductive pads also are coupled to a substrate comprising an apparatus for extracting heat from the thermally conductive pads. The apparatus for extracting heat from the thermally conductive pads preferably comprises one or more metallic planes. A module cover having a thermally conductive path formed therein also may be coupled between the apparatus for extracting heat and a heat sink to further aid in heat removal from the semiconductor device. Thermally conductive pads may be coupled between the semiconductor device and I/O pins of the substrate to improve heat dissipation via the I/O pins.

Abstract: A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection.

Abstract: A dichroic phase shift photo mask (20) is formed by forming a dichroic film (24) over a transparent substrate (11) and selectively etching the dichroic film (24) to form phase shifters (35, 38) of the mask (20). Typically, the mask (20) also includes light blocking structures (34, 36, 37, 39) over the substrate (11). The dichroic film (24) has a high transmittance to a light used in a photolithography process, during which the phase shifters (35, 38) generate interference patterns and significantly increase the image resolution of the light blocking structures (34, 36, 37, 39). The dichroic film (24) has a low transmittance to a light used in inspecting the mask (20). The inspection of the mask (20) includes illuminating the mask (20) with a light beam, and identifying the phase shifters (35, 38) by observing the intensity of the light transmitted through the mask (20).

Abstract: Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed. A first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same joining plane has a second characteristic (e.g., a second height greater than the first height). The first and second characteristics of the chip-on-chip interconnections allow for chip-on-chip connections to other packages, substrates or chips of different levels and/or compositions.

Abstract: Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed. A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging.

Abstract: A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.