Abstract: A gap conducting structure for an integrated electronic circuit that functions as an electronic fuse device and that is integrated as part of the semi-conductor chip wiring for providing over-current and thermal runaway protection. The gap conducting structure includes one or more air gap regions of predefined volume that fully or partially exposes a length of interlevel conductor layer in an IC. Alternately, the air gap region may wholly located within the dielectric region below a corresponding conductor and separated by insulator. When functioning as a fuse, the gap region acts to reduce thermal conductivity away from the exposed portion of the conductor enabling generation of higher heat currents in the conducting line with lower applied voltages sufficient to destruct a part of the partially exposed/fully exposed conducting line, thus preventing thermal runaway and over-current condition.

Abstract: A process and apparatus for depositing thin films onto a substrate. The process comprises mounting a wafer onto a wafer chuck and pumping a cryogenic fluid through the chuck which cools the wafer chuck and the wafer to a temperature below about +20° C. A thin film is then deposited over the cooled wafer using a sputter deposition process while maintaining the temperature of the wafer chuck and the wafer below about +20° C. The preferred embodiment of the present invention includes the use of liquid nitrogen as the cryogenic fluid, and copper as the material to be deposited through the sputtering process. In addition, the preferred embodiment cools the wafer chuck and the wafer to a temperature of about −100° C. The apparatus includes the physical vapor deposition vessel, the wafer chuck, the source of material to be deposited, the wafer, and the cooling line which passes through the wafer chuck to carry the cooling fluid to the chuck.

Abstract: A micromechanical sensor probe for a scanned-probe tool includes a silicon cantilever and a silicon tip physically attached to the cantilever. The micromechanical sensor probe has a coating of a refractory metal silicide formed at least on the tip. Titanium silicide is preferred. The probe also has a layer of refractory metal nitride formed entirely over the refractory metal silicide.

Abstract: A method is provided for treating a plurality of semiconductor substrates using the same aqueous SC-1 solution which solution removes and/or inhibits contamination of the semiconductor surfaces by metallic ions present in the solution or on the substrate surface comprising a basic solution containing hydrogen peroxide and an oxidation-resistant chelating additive such as CDTA in an amount effective to provide the desired treatment results. The SC-1 solution may be the conventional 5:1:1 (water:NH4OH:H2O2) solution or a dilute solution such as a 5:x:1 to 200:x:l solution wherein x is 0.025 to 2.

Abstract: A trench storage dynamic random access memory cell with vertical transfer device can be formed in a wafer having prepared shallow trench isolation. Vertical transfer device is built as the deep trenches are formed. Using square printing to form shallow trench isolation and deep trenches, allows for scaling of the cell to very small dimensions.

Abstract: A static resistant reticle for use in photolithography having optimal transmission and reduced electrostatic discharge. The reticle comprises a substrate, a patterning layer, and two layers of material having a first refractive index and a second refractive index wherein the first refractive index is greater than the second refractive index and at least one of the layers is conductive. The refractive indices and thickness of the layers are matched to create an anti-reflective coating. The anti-reflective coating optimizes transmission of light through the reticle substrate to about 98.0% to about 99.5% at a wavelength of about 360 nm to about 370 nm. The conductivity of at least one of the layers reduces electrostatic discharge further improving delineation of the pattern projected onto a silicon wafer of a semiconductor device. Preferably, the anti-reflective coating comprises two or more layers of cermet material.

Abstract: A non-motorized polishing pad conditioner and cleaner having a free-wheeling conditioner head with a plurality of channels to direct the flow of a cleansing fluid; a hollow shaft connected to a fluid source; and a conditioning pad to facilitate loosening the debris found on a polishing pad wherein the pad conditioner and cleaner is self-propelled upon contact with a rotating polishing pad. A cantilever may be used to attach the conditioner and cleaner adjacent to the polishing apparatus. The cantilever may contain a motorized element for extending and retracting the conditioner and cleaner over the radius of a polishing pad such that the entire surface of the polishing pad may be conditioned and cleaned. A method of conditioning and cleaning a polishing pad while simultaneously polishing a silicon wafer is also described.

Abstract: A method and apparatus for repairing black dot defects connected to a circuit pattern in photomasks such as a photomask having a patterned chromium film on a glass substrate comprises using an energy source in the form of an energy beam to first sever the connected black dot defect from the chrome pattern forming a space between the defect and the chrome pattern. The remaining severed black dot defect is then removed using the same or different energy beam to remove the remainder of the chrome defect. An apparatus for removing black dot defects and photomasks produced by the method and apparatus of the invention are also provided.

Abstract: Disclosed is a method and apparatus for polishing a semiconductor wafer. This invention describes a novel in situ method for eliminating residual slurry and slurry abrasive particles on the wafer. A reactant is added to the slurry during the end of the Chemical Mechanical Polish (CMP) process to dissolve the slurry and etch the abrasive particles.

Abstract: A packaging assembly for semiconductor memory modules using synchronous clocking signals distributed to each module within a package. The clock distribution network on the assembly is characterized by including a transmission line termination means, preferably a resistor, coupled immediately adjacent to one of the assembly input pins.

Abstract: A colloidal silica slurry containing triethanolamine is used in a chemical mechanical polishing process to polish multiple material substrates, such as silicon wafers containing silicon oxide where a thin underlayer of silicon nitride is used as a stop layer. The colloidal silica slurry containing triethanolamine is capable of achieving an oxide to nitride selectivity during polishing up to a demonstrated ratio of 28:1.

Abstract: Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.

Abstract: A method is provided for making sublithographic structures, such as programmed defect masks. The method comprises the steps of forming a layer of base material on a substrate, the base material being selectively definable from the substrate, forming a layer of photosensitive material over the layer of material, selectively exposing a plurality of image segments in the photosensitive material in which segments are offset from each other by a sub-lithographic dimension in a first direction and a different dimension in a second direction and a sub-plurality of the segments pass over the layer of base material, and developing the photosensitive material to expose the layer within the sub-plurality of segments. Also provided is the resulting programmed defect mask with defects under 0.1 .mu.m in size.

Abstract: A fixture for holding a semiconductor die against an abrasive media for the purpose of thinning the die is described. The fixture provides means for aligning the back of the die to a reference plane that is coplanar with the plane of the abrasive and is in contact with the abrasive media during the thinning process.

Abstract: On-chip ESD protection for semiconductor chips with mixed-voltage interface applications and internal multiple power bus architecture are described. ESD robustness in shallow trench isolation 0.50- and 0.25-micron channel-length CMOS technologies is presented in the form of ESD structures and circuits including hybrid three-rail and mixed voltage interface embodiments.

Abstract: The present invention is directed to a method for adding fill shapes to a chip in a manner which accommodates a wide range of within-chip pattern density variations and provides a tight pattern density control (i) within a chip and (ii) from chip to chip. The present invention imposes a grid over a chip design pattern, wherein each section of the grid contains a portion of the chip design. A pattern density is then determined for each section of the grid, based on that portion of the chip design pattern which lies within the particular grid section. The results of the pattern density determination are used to determine where to place fill shapes in the chip design in order to increase a density value in each section of the grid to that of a target density value. The method and apparatus of the present invention provide a best fit approximation to the desired pattern density consistent with a set of layout rules for the level being patterned.

Abstract: Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.

Abstract: A polishing pad and method of polishing with a chemical mechanical planarization apparatus includes providing a bulk polishing pad material having a front polishing surface side and a back side. The polishing pad further includes a polishing pad wear indicator for indicating a polishing pad wear during a life cycle of the polishing pad. The polishing pad wear indicator is formed on the back side of the bulk polishing pad material.

Abstract: A brush conditioner for a semiconductor wafer cleaning tool including a pair if opposed, rotating flexible brushes. The conditioner is a wing-like structure having a leading edge and a trailing edge. The leading edge is forced against the rotating brushes flexing them to assist in removal of foreign material. The trailing edge tapers to a point and provides stability to the wing.

Abstract: A desired reagent is delivered to a workpiece undergoing a chemical mechanical polishing process with a chemical mechanical planarization apparatus. A slurry and polishing pad are provided for the polishing process. Reagent containing microcapsules are also provided, the microcapsules encapsulating a desired reagent. The workpiece is polished with a combination of the slurry, the polishing pad, and the microcapsules, wherein the encapsulated reagents are controllably released during the polishing step via manipulation of a polishing parameter. In one embodiment, the microcapsules are included in the slurry. In an alternate embodiment, the microcapsules are embedded within the polishing pad.