Abstract: An integrated circuit device structure having probe pad extensions in electrical communication with the wire bond pads and a method for performing failure analysis thereon. The invention provides an improved probing system for wire bond packages such that neither the wire nor the wire bond from the pads on the chip surface need be removed during testing procedures. Included in the integrated circuit device is a plurality of conductive pads having a first area for receiving a wire bond and a second area for receiving a probe, wherein the second area abuts, and is an electrical communication with the first area.

Abstract: A method of preparing an x-ray mask comprising providing a substrate, and applying sequentially to a surface of the substrate i) an etch stop layer resistant to etchant for an x-ray absorber, and ii) an x-ray absorber layer. The method then includes removing a portion of the substrate below the layers to create an active region of the substrate above the removed portion of the substrate and an inactive region over remaining portions of the substrate, applying a resist layer above the absorber layer, and exposing a portion of the resist layer using electron beam irradiation and developing the resist layer to form a latent mask image over the active region of the substrate.

Abstract: A recessed bond pad within an electronic device on a substrate, and associated method of fabrication. The electronic device includes N contiguous levels of interconnect metallurgy, with level N coupled to the substrate. A first group of metallic etch stops is formed at level M≦N, and a second group of metallic etch stops is formed at level M−1. The second group conductively contacts the first group in an overlapping multilevel matrix pattern. A recessed copper pad is formed at level K≦M−2. A cylindrical space that encloses the metal pad encompasses levels 1,2, . . . , M−1 above the first group, and levels 1,2, . . . , M−2 above the second group. Dielectric material in the cylindrical space is etched away, leaving a void supplanting the etched dielectric material, and leaving exposed surfaces of the cylindrical space. The copper pad is exposed and recessed within the cylindrical space.

Abstract: A ferric nitrate-alumina based slurry useful for Chemical-Mechanical-Polishing of tungsten metallurgy and silica based oxides on semiconductor substrates in which the suspension and stability of abrasive material in the slurry is essentially stable. The slurry formulation is balanced to provide low residue of foreign material after polishing and due to its reduced ferric nitrate concentration will be less corrosive than prior art slurries. The recipe for the slurry includes of a 30% wt silica suspension, about 800 ml of 40% by wt ferric nonahydrate, liters and enough 70% wt nitric acid to adjust the pH of the slurry to about 1.2 to 1.4.

Abstract: A method of detecting the presence of a brush used in a semiconductor wafer cleaner for post-CMP processing is described. Semiconductor wafers are loaded into the wet environment of the wafer cleaner, affixed to a rotatable fixture and rotated at high speed. The rotatable fixture is effectuated by a servo motor linked to a servo controller and a torque monitor. A first torque on the rotating wafer is calculated prior to the start of the brush cleaning cycle. During the brush cleaning cycle, as the brush within the brush cleaner contacts the rotating wafer, the torque on the wafer increases and a second torque is calculated. If, during the brush cleaning cycle, the second torque calculation is substantially equal to the first torque calculation, the brush cleaner is not contacting the wafer and cleaning has not progressed. A tool user can be notified to reaffix the brush within the cleaner.

Abstract: A method of reworking copper metallurgy on semiconductor devices which includes selective removal of insulator, selective removal of copper, non-selective removal of copper and insulator followed by the redeposition of an insulating copper barrier layer and at least one metallurgical interconnect layer.

Abstract: A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.

Abstract: A method and structure for blowing a fuse including removing an insulator above a fuse link and etching the fuse link.

Abstract: A structure and method for polishing a device include oscillating a carrier over an abrasive surface (the carrier bringing a polished surface of the device into contact with the abrasive surface, the oscillating allowing a portion of the polished surface to periodically oscillate off the abrasive surface), optically determining a reflective measure of a plurality of locations of the polished surface as the portion of the device oscillates off the abrasive surface and calculating depths of the locations of the polished surface based of the reflective measure.

Abstract: A semiconductor wafer rework process sideways etches an underlying layer of metal to remove a difficult to etch upper layer of metal without substantially etching that upper layer and without damaging permanent layers of the wafer. If the underlying layer of metal is TiW and the permanent layer is aluminum, the TiW layer can be sideways etched with a hydrogen peroxide and ammonium hydroxide solution that does not damage aluminum lines that are permanently on the wafer. Thus, difficult to remove intermetallic layers, such as tin-copper or chrome-copper, that are located on an underlying layer of TiW, can be successfully removed without danger of damaging permanent aluminum metallization of the wafer.

Abstract: Non-aqueous cleaning compositions capable of removing cured polyimides and other polymers from a metal circuitry containing substrate such as a semiconductor device for rework and other purposes without any significant adverse affect on the circuitry are provided consisting essentially of alkanolamines, preferably monoethanolamine or monoethanolamine-diethanolamine mixtures and optionally with a solvent such as NMP in an amount less than about 50% by weight. A method is also provided for removing polyimide coatings and other polymers from semiconductor devices using the cleaning compositions of the invention.

Abstract: A method and structure for manufacturing Charge-Coupled-Device (CCD) image pick-up devices. The method bonds a first wafer with a second wafer. The first wafer has a CCD layer on a first substrate, wherein the CCD layer includes a plurality of CCD pick-up image arrays. The CCD layer is thin, preferably in a range of 5 to 20 microns, while the substrate is relatively thicker (e.g., 300 microns). The first wafer also includes first conductive pads arranged in a pattern on a surface of the CCD layer such that each CCD array is conductively coupled to a plurality of the first conductive pads. The second wafer has a second substrate that includes a semiconductor material such as silicon, and second conductive pads according to the pattern on a surface of the second substrate. The first wafer is bonded with the second wafer to form a wafer composite, wherein the first conductive pads are joined to the second conductive pads in accordance with the pattern.

Abstract: An electronic switch circuit switches out bad decoupling capacitors on a high speed integrated circuit chip. The circuit comprises a control device that operates in the subthreshold or off device state to detect leakage in a decoupling capacitor. This control device operates in a low impedance state if the capacitor is good and in a high impedance sate if the capacitor is bad. A feedback circuit is connected from an internal node of the capacitor to a gate of the control device so that once a state of the capacitor is detected it can be stored on the gate of the control device. A single external signal source shared by a group of capacitors activates the control device to detect leakage in the capacitor. The circuit operates to switch out capacitors that fail during normal operation.

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of a chip at increased frequencies.

Abstract: A multilayer interconnected electronic component having increased electromigration lifetime is provided. The interconnections are in the form of studs and comprise vertical side walls having a refractory metal diffusion barrier liner along the sidewalls. The stud does not have a barrier layer at the base thereof and the base of the stud contacts the metallization on the dielectric layer of the component. An adhesion layer can be provided between the base of the stud and the surface of the metallization and the adhesion layer may be continuous or discontinuous. The adhesion layer is preferably a metal such as aluminum which dissolves in the stud or metallization upon heating of the component during fabrication or otherwise during use of the component. A preferred component utilizes a dual Damascene structure.

Abstract: A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETS; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device's channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer.

Abstract: Methods for forming metal interconnects are provided. An insulating layer is formed on top of a substrate and a via is formed in the insulating layer reaching to the substrate. The via then is filled with a sacrificial material and a trench aligned over the via is formed by removing an upper portion of the insulating layer and an upper portion of the sacrificial material within the trench. The sacrificial material preferably is selected to etch faster than the insulating layer. After forming the trench, remaining sacrificial material in the via is removed and the via and the trench are filled with a conductive material. In addition to a single insulating layer, the insulating layer on top of the substrate may comprise a first insulating layer formed on top of the substrate, an etch stop layer formed on top of the first insulating layer and a second insulating layer formed on top of the etch stop layer.

Abstract: A ferric nitrate-alumina based slurry useful for Chemical-Mechanical-Polishing of tungsten metallurgy and silica based oxides on semiconductor substrates in which the suspension and stability of abrasive material in the slurry is essentially stable. The slurry formulation is balanced to provide low residue of foreign material after polishing and due to its reduced ferric nitrate concentration will be less corrosive than prior art slurries. The recipe for the slurry includes of a 30% wt silica suspension, about 800 ml of 40% by wt ferric nonahydrate and enough 70% wt nitric acid to adjust the pH of the slurry to about 1.2 to 1.4.

Abstract: The advantages of the invention are realized by a chip-on-chip module having at least two fully functional chips, electrically connected together, and a chip-on-chip component connection/interconnection for electrically connecting the fully functional chips to external circuitry.

Abstract: A method and apparatus for reducing the risk of environmental contamination from mercury spillage during carry over between processing tanks during the gold ball bond removal process by providing a self-contained, compact, environmentally safe system for use with toxic chemicals and liquids. The present invention provides a self-contained, integrally molded enclosure upper and lower chambers separated by a partition. The partition has a plurality of stations integrally formed therein, each of which is capable of containing a chemical liquid. The method comprises dipping a slide containing the semiconductor chip first into a toxic liquid, then into a first decontamination station and finally into a second decontamination station.