Abstract: The invention provides a method for providing an integrated circuit (6) having a substantially uniform density between parts (10, 12, 14 and 16) of the IC that are non-orthogonally angled. In particular, the invention provides fill tiling patterns (32, 34) oriented substantially parallel to electrical structure regardless of their angle. A method of electrical analysis based on this provision is also provided as is a related program product.

Abstract: Digest screen display content deciding means selects display elements belonging to respective regions of a document based on display priorities of the display elements, which are obtained by digest screen display priority information creating means, and decides selected display elements as display content of a digest screen under a condition where a total display area does not exceed a required display area. A merging relationship among the regions is set based on layout information for the regions, created by digest screen region layout information creating means. Display content deciding means decides the display content of a detail screen based on the merging relationship among the regions, and creates a digest of the detail screen based on control information created by control information creating means. Moreover, digest screen display content changing means changes the display content of the digest screen in response to an operation of a user.

Abstract: A robust means of watermarking a digitized image with a highly random sequence of pixel brightness multipliers is presented. The random sequence is formed from ‘robust-watermarking-parameters’ selected and known only by the marker and/or the marking entity. A watermarking plane is generated which has an element array with one-to-one element correspondence to the pixels of the digitized image being marked. Each element of the watermarking plane is assigned a random value dependent upon a robust random sequence and a specified brightness modulation strength. The so generated watermarking plane is imparted onto the digitized image by multiplying the brightness value or values of each pixel by its corresponding element value in the watermarking plane. The resulting modified brightness values impart the random and relatively invisible watermark onto the digitized image. Brightness alteration is the essence of watermark imparting.

Abstract: Data packet buffering system comprising a data buffer for buffering data packets, a first counter (24) preloaded with the data packet size (32) and decremented at each read clock signal of a number of logical units corresponding to the width of the output bus (18), a second counter (28) preloaded with the data packet size and decremented at each write clock signal of a number of logical units corresponding to the width of the input bus (14), the decrementation of the second counter being started at the same time as the decrementation of the first counter by a start counter signal (38), and a threshold unit (52) for determining the minimum threshold from the contents of the second counter when the first counter has reached zero and providing the minimum threshold to a buffer management logic unit a buffer management logic unit (22) providing write grant signals when data may be read from the data buffer and sent to an output device.

Abstract: An apparatus for testing a memory of an integrated circuit for a defect. The apparatus includes a test unit for testing a redundant memory element only when the redundant memory element has been enabled to replace a failed memory element.

Abstract: A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a second resist layer with the image of the gate pads and local interconnect and then etching the polysilicon with the pattern of the gate pads and local interconnect, thereby reducing the number of diffraction and other cross-talk from different exposed areas.

Abstract: A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial polymer containing silicon that is deposited over a gate conductor layer and covered by a cover layer. The sacrificial polymer layer is patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the polymer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

Abstract: Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.

Abstract: In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.

Abstract: Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a seed layer into the pattern formed by the ILD and PEL, and then plating copper on the seed layer. The PEL serves to decrease the resistance across the wafer so to facilitate the plating of the copper. The PEL preferably is an optically transparent and conductive layer.

Abstract: A method and system for detecting and managing an error detected in an iSCSI (Internet Small Computer System Interface) PDU (Protocol Data Unit) by using a RDMA (Remote Direct Memory Access) dedicated receive error queue for error recovery.

Abstract: The invention relates to a method of structuring of a substrate by providing a polymerization starter layer on the substrate, applying a radiation field on the polymerization starter layer for selectively reducing a density of polymerization starters of the polymerization starter layer, applying monomers and then polymerizing of the monomers, the polymerization being initiated by the starters of the polymerization starter layer, and structuring the substrate using the polymerized monomers as a mask.

Abstract: The present invention provides a thin film transistor structure in which at least a trench is formed in an insulating polymer film formed on a substrate. In the thin film transistor structure, a trench formed in the insulating polymer film accommodates a gate wiring constituted of a plurality of conductive layers. Provided also are a method of manufacturing the thin film transistor structure, and a display device including a thin film transistor array composed of the thin film transistors constituted as described above.

Abstract: Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.

Abstract: A high-density DRAM in a MTBL method which reduces interference noise between bit lines is provided. Duplication of sense amplifiers (SA) and bit switches (BSW) in a conventional MTBL method is eliminated, and one line of sense amplifiers and bit switches (BSW/SA) is arranged between cell areas. Specifically, arrays are horizontally moved and vertically cumulated so as to reduce the areas. Bit line pairs to be connected are alternately interchanged above and below, every one horizontally aligned sense amplifier (SA) such that there is only one bit line pair connected to each sense amplifier. Bit lines of a bit line pair 11 cross at one place on the way, and from the cross, a space between the bit lines is wider. Further, bit lines of a bit line pair 16 do not cross each other, and a space between the bit lines is wider on the way.

Abstract: Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so as to form nonplanar metallic structures. Surrounding each of the nonplanar metallic structures is a ring of dielectric material which provides a hard stop during probing of the bond pad so as to limit the amount of bond pad that can be removed during probing.

Abstract: The invention relates to a method of structuring of a substrate by providing a polymerization starter layer on the substrate, applying a radiation field on the polymerization starter layer for selectively reducing a density of polymerization starters of the polymerization starter layer, applying monomers and then polymerizing of the monomers, the polymerization being initiated by the starters of the polymerization starter layer, and structuring the substrate using the polymerized monomers as a mask.

Abstract: Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

Abstract: A method to electrolessly plate a CoWP alloy on copper in a reproducible manner that is effective for a manufacturable process. In the method, a seed layer of palladium (Pd) is deposited on the copper by an aqueous seeding solution of palladium acetate, acetic acid and chloride. Thereafter, a complexing solution is applied to remove any Pd ions which are adsorbed on surfaces other than the copper. Finally, a plating solution of cobalt (Co), tungsten (W) and phosphorous (P) is applied to the copper so as to deposit a layer of CoWP on the Pd seed and copper.

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.