Abstract: A method wherein optical fibers in a silicon connector are joined to a second optical component. The silicon connector is etched back with a dry etchant that is highly preferential for silicon to thereby etch the silicon connector much more than the optical fiber. After etching, the optical fibers protrude beyond the silicon connector so that they may be easily joined to the second optical component. Also disclosed is an optical fiber assembly made according to this method.

Abstract: A method of fabricating an integrated circuit in and on a semiconductor substrate with deep implantations by applying a scattered ion capturing layer in the resist mask opening to capture any implanted ions scattered in the resist and deflected out of the resist into the mask opening to prevent these ions from reaching the semiconductor substrate and affecting the concentration of ions at the edge of the mask and thus the performance of the integrated circuit.

Abstract: A method and apparatus for separating a chip from substrate where the chip is attached to the substrate by solder connections to form an assembly involve applying a loading force to drive a coil spring biased shearing element comprising a slide block with carrying a shearing blade into a loading position. Load the assembly of the substrate and the chip into a fixture with a window therethrough for the chip with the shearing blade in contact with the chip. Remove the loading force to arm the shearing blade to apply a shearing force from the shearing blade to the chip. Heat the solder connections of the assembly in the fixture to a predetermined temperature, preferably below the melting temperature of the solder at which shearing of the solder connections occurs. The shearing blade comprises a slidable plastic blade backed up by a metal blade.

Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.

Abstract: An alignment mark structure for use upon a semiconductor substrate is disclosed. In an exemplary embodiment, the alignment mark structure includes a plurality of segments arranged in an alignment pattern, with each of the plurality of segments being formed from a base pattern created on the substrate. The base pattern includes a plurality of sizes, wherein each of the plurality of sizes of the base pattern is repeated throughout an entire length of each of the plurality of segments.

Abstract: A memory storage system is disclosed. In an exemplary embodiment, the memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements.

Abstract: An integrated circuit having a charge pump is tested for excessive current draw by counting the number of times the charge pump cycles in a test interval, storing the result in a register that is used for another purpose during operation and comparing the result with a reference number representing acceptable leakage, thereby identifying latent defects that may become a cause of failure as well as short circuits.

Abstract: A method of processing greensheets for use as microelectronic substrates comprises providing a greensheet having a width, a length and a thickness, bonding to the greensheet, within the greensheet width and length, a frame adapted to constrain movement of the greensheet within the frame, processing the greensheet and bonded frame, and removing the frame from the processed greensheet. The processing of the greensheet and bonded frame may include punching vias in the greensheet, filling the vias in the greensheet with conductive material, patterning the greensheet by applying conductive paste to the vias and greensheet surface, stacking the patterned greensheet and bonded frame with at least one other patterned greensheet and bonded frame, and laminating the greensheets. The frame is preferably removed from the processed greensheet after laminating the greensheets, and before the laminated greensheets are subsequently sintered.

Abstract: A multichip module including a frame having contacts suitable for making an electrical connection with an article, preferably a printed wiring board or similar, which is the next level of packaging, a multilayer thin film structure mounted to the frame, and semiconductor devices mounted to the thin film structure with at least one semiconductor device on each of two opposed sides of the thin film structure. The thin film structure includes arrays of pads on opposed surfaces of the thin film structure for connecting the thin film structure to the semiconductor devices and the frame. The thin film structure further includes wiring for chip to chip connectivity and for connecting to the frame.

Abstract: In the present invention an electronic package assembly includes an integrated circuit positioned on a substrate. The substrate has substantially horizontal layers including horizontal signal wires having vertical thicknesses and resistance. In a preferred embodiment, first and second vertical thicknesses of the signal wires alternate from the top to the bottom of the substrate such that the signal wires with greater vertical thicknesses have lower resistance than the signal wires would typically have. A plurality of substantially vertical conductive vias traverse the horizontal layers such that the vertical conductive vias connect to the integrated circuit and connect with at least one of the horizontal signal wires. A circuit board positioned beneath the substrate includes connection members for connecting with, and terminating the vertical conductive vias.

Abstract: A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench.

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 &mgr;m) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.

Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

Abstract: A multi chip module substrate arranged with repair vias and repair lines extending between repair vias of the chip sites of the module by which repairs can be effected to overcome defects in the module circuits and a method for effecting the repairs of defects in the circuits of this module. A defect can occur in any one of a first signal via, a second signal via, and a circuit line extending between and intended to electrically connect the first signal via and the second signal via. After a defective circuit is identified, the signal vias of the circuit are isolated. Then, the first signal via of the defective circuit is electrically connected to that repair via of the chip site having the first signal via that is connected to that repair via of the chip site having the second signal via and the second signal via of the defective circuit is electrically connected to that repair via of the chip site having the second signal via that is connected to that repair via of the chip site having the first signal via.

Abstract: A method in which an alignment tool consisting of a nest and guide tool is used to align an LGA module in the nest and then the LGA module is removed from the nest and aligned with a circuit card by the use of the guide tool.

Abstract: An integrated circuit module, a land grid array module, and a method for forming the module, include a substrate, which mounts one or more chips or discrete electronic components, and a cap for covering the substrate, and including at least one protrusion coupled to the cap for limiting the amount of flexing of the substrate during actuation. The at least one protrusion can be either rigidly fixed to the cap or adjustably inserted through the cap.

Abstract: As disclosed herein, a method is provided for simultaneously patterning features having a first width in a first portion such as a logic portion of an integrated circuit, and having a second width in a second portion such as an array portion of an integrated circuit. The method includes depositing a feature layer over a substrate and a hardmask material layer thereover. Photoresist patterns are then formed in the first and second portions with a critical dimension mask, and are then used to etch the hardmask material layer into hardmask patterns. Sidewall spacers are provided on sidewalls of the hardmask patterns in the second portion. Then, the feature layer is simultaneously etched in both first and second portions, using the hardmask patterns in the first portion to define features having a first width, and using the hardmask patterns and the sidewall spacers in the second portion to define features having a second width.

Abstract: A gas isolation box including an enclosure; a number of gas sticks contained within the enclosure, each gas stick including a process gas section comprising a first process gas inlet valve for gating the flow of a process gas into the gas stick; a purge gas section including a purge valve for gating the flow of a purge gas into the gas stick; and an evacuation section including a first evacuation valve for gating the exiting of a process gas or a purge gas from the gas stick, a bleed valve which in a closed position allows process gas to bleed through the bleed valve and in an open position allows purge gas to freely flow through the bleed valve, and a vacuum generator module which pulls a vacuum to evacuate a purge gas or any remaining process gas in the gas stick or the tool through the first evacuation valve and the bleed valve and out from the gas stick to an exhaust stream.

Abstract: The present invention discloses a method and apparatus for correctly positioning the text of a hypertext markup language (html) file on a display screen linked to a computer such that there are no partial lines of text displayed and without the re-display of text that was displayed on a previous screen. By correctly positioning the text on the display screen, even when the user scrolls the text backwards and forwards, only entire lines of text are displayed which makes reading the text on the screen much more user friendly. By locating the html tags within the html source file, the number of lines of text in the file are determined and subsequently assigned to a screen row within the display screen such that only entire lines of text are displayable.