Abstract: A field-effect transistor possesses improved electrostatic discharge characteristics. The transistor (10), formed in a p-type semiconductor substrate, comprises a gate (16) that forms a channel between two adjacent n-regions (12 and 14). At least one of the n-regions (12) has an n-well (22) below and centered about a contact pad (18). The n-well (22) has a second lower concentration of n-type impurities than either of the n-regions.

Abstract: A high voltage power transistor cell is developed that provides improved RDSon performance without sacrificing breakdown performance through utilization of trench based transistor technology. A source, drain and trench are formed within a substrate. A gate is formed on the surface over a spacing between the source and the trench. A drift region is formed around the trench. An isolation region may optionally be added allowing electrical isolation between the source and the substrate. The lateral current flow feature allows multiple high voltage power transistors, electrically isolated from one another, to exist on a single semiconductor chip. The drift region formed around the trench provides RESURF transistor characteristics without sacrificing die area.

Abstract: A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semiconductor and the substrate 12 may be silicon, quartz, gallium arsenide, glass, ceramic, metal or polyimide. A neutral (undoped) layer 16 of radiation sensitive material is formed over the doped layer 14. First and second source/drain regions 18 and 20 are formed in the neutral layer 16 and extend to a top portion of the doped layer 14. A gate region 22 is formed in a top portion of the neutral layer 16 between the first source/drain region 18 and second source/drain region 20 such that a channel region 24 is formed in the doped layer 14 beneath the gate region 22.

Abstract: An integrated circuit includes conductive elements and a radiation sensitive material interposed between the conductive elements and dosed to different conductivities in different portions thereof. Another aspect is a process of integrated circuit fabrication including steps of depositing a radiation sensitive material as a layer and variably dosing it with radiation to establish areas of higher and lower resistivity in the layer. A printed wiring board includes radiation sensitive material and the board further has a conductor layer affixed to the base. A transistor has a radiation sensitive material dosed to have two conductive regions separated by a gap of a lower conductivity in the radiation sensitive material, and a conductive substance deposited over the gap. These elements are useful in smart power devices, digital computers, controllers and electronic applications generally. Other devices, systems and processes are disclosed.

Abstract: A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semiconductor and the substrate 12 may be silicon, quartz, gallium arsenide, glass, ceramic, metal or polyimide. A neutral (undoped) layer 16 of radiation sensitive material is formed over the doped layer 14. First and second source/drain regions 18 and 20 are formed in the neutral layer 16 and extend to a top portion of the doped layer 14. A gate region 22 is formed in a top portion of the neutral layer 16 between the first source/drain region 18 and second source/drain region 20 such that a channel region 24 is formed in the doped layer 14 beneath the gate region 22.

Abstract: A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).

Abstract: A semiconductor 110 device includes an array of like base cells wherein each base cell includes at least one source 132 and at least one drain 130 region formed in a semiconductor substrate. At least one gate 126 is formed over and insulated from a channel region 118 which separates the source 132 and drain 130 regions. An insulating layer 190 overlies the structure. A plurality of contacts are formed in the insulating layer in a plurality of substantially parallel; evenly spaced grid lines G1-G5. In addition, at least one additional contact 150 formed between two adjacent ones G2 and G3 of the substantially parallel grid lines is formed. A plurality of interconnect lines 142 and 144 are formed over the insulating layer such that each contact is connected to at least one of the interconnect lines. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.

Abstract: A magnetic apparatus (10) is provided having a bottom plate (12), a top plate (14), a first magnet guide (16), a second magnet guide (18) and a magnet member (20) which is slidable upon a slide axis (22) through apertures (40) and (54) of first magnet guide (16) and second magnet guide (18) respectively. The magnetic apparatus (10) is shown in a closed position in FIG. 1 for use in conjunction with a reed switch (86) (see FIG. 3) mounted on bottom plate (12). In the closed position magnet member (20) is close enough to the reed switch (86) to magnetically toggle reed switch (86) and thus electrically toggle electrical circuit (100). When the magnetic apparatus (10) is moved in three-dimensional space so that reference plane (24) is changed with respect to gravity line (26) to a sufficient degree, then magnet member (20) will shift along slide axis (22) toward second magnet guide (18).

Abstract: In one embodiment, a non-volatile memory structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region. 21. A floating gate 13 is formed over and insulated from the channel region 21 and a control gate 14 is formed over and insulated from the floating gate 13. A lightly doped region 20 is formed in the channel 21 beneath the floating gate 13 and adjoining the source region 11. The lightly doped region 20 is spaced from the surface of said substrate 8. Other embodiments and processes are also disclosed.

Abstract: An optical system for directing light to a spatial light modulator 16 (e.g., a digital micro-mirror device) is disclosed herein. This system can be used with displays, printers or cameras. The system includes a first light generating apparatus 30a for generating a first beam of light and a second light generating apparatus 30b for generating a second beam of light. A first lens 36a directs the first beam of light toward the spatial light modulator 16 at a first angle. Also, a second lens 36b directs the second beam toward the spatial light modulator 16 at a second angle. The system also includes an apparatus 34 which redirects either the first or the second beam of light away from the spatial light modulator 16.

Abstract: A semiconductor storage device is disclosed herein. A semiconductor substrate 1 has a first conductive type. A first groove is provided in this semiconductor substrate 1. A second groove 20, which is deeper than the first groove, is provided so as to be stacked within the first groove. A MOS transistor which include first and second regions 22 and 23 is connected to an accumulating electrode 133. The accumulating electrode 133 is disposed in the second groove 20 and separated from it by an insulating film 124. An electrode 143 is provided on the accumulating electrode 133 and separated therefrom by a capacitor insulating film 135. The electrode 143 is buried in the first and second grooves.

Abstract: A closed loop, (networked) information management and security system which provides a secure, end-to-end fully automated solution for controlling access, transmission, manipulation, and auditability of high value information comprising an RFID transponder badge 302 and an RF reader transceiver 315 which is associated with a host peripheral or a network. The RF reader transceiver 315 automatically identifies and verifies authorization of the RFID transponder badge holder via a "handshake" prior to allowing access to the host peripheral. The energy generated by the transmission of the interrogation signal from the RF reader means 315 provides a power source which is accumulated and then used to activate a transponder 304 response from the RFID transponder badge 302. The RF reader/transceiver 315 writes the access transaction on either the RFID transponder badge 302 and/or the host peripheral database or the network controller.

Abstract: A thin film transistor and method for forming the same are disclosed. The transistor comprises a gate conductor (14) and a gate insulator (16). A semiconductor channel layer (18) is formed adjacent the gate insulator (16). A mask block (22) is formed covering a channel region (30) in the channel layer (18). A source region (26) and a drain region (28) are formed in the channel layer (18) adjacent opposite ends of the mask block (22). Conductive bodies (32) and (34) are formed in contact with source region (26) and drain region (28), respectively. Electric contacts (42) and (44) are then formed in contact with conductive bodies (32) and (34), respectively.

Abstract: The present invention discloses an electromagnetic device which includes a magnetic flux producing apparatus for producing a magnetic flux path loop. The magnetic flux producing apparatus preferably comprises a magnetic core 20 surrounded by electrical windings 22. A strip of electrically conductive material 24 is disposed such that it passes through the magnetic flux path loop and overlies the windings 22. The strip 24 has a width which is substantially greater than its thickness. The device may further include an antenna 16 which is electrically coupled to the strip 24.

Abstract: Apparatus and method for producing a flexible antenna suitable to be incorporated in a badge or similar object. The antenna comprises electrical windings (28, 38) surrounding a flexible antenna core (26, 36). The antenna core (26, 36) is of a material having a high quality factor formed of a plurality of mutually insulated, longitudinally extending chains of magnetic soft material of high .mu.. According to one embodiment, a powder of small particles of a magnetic soft material of high .mu. is mixed with a synthetic resin so that a high saturation of magnetic material in the mixture is formed in a vacuum. The mixture is cured in a strong magnetic field so that the particles form chains (18A, 18B, 18C) of the particle parallel to the applied magnetic field.

Abstract: An output buffer with a slew rate that is load independent is comprised of an output buffer (14) that is connected to an output terminal (12). The output buffer (14) is controlled such that it can drive a load (18) with different drive levels by changing the transconductance internal thereto. The transition on the input to the buffer (14) is passed through an intrinsic delay block (34) and variable delay block (40) to provide a delay signal on a node (42). A first phase detector latch (50) with a first threshold voltage compares this transition with the transition on the output terminal (12). A second phase detector latch (60) with a second threshold voltage, also compares this delayed transition with that on the output terminal (12). If both of the latches (50) and (60) indicate that the delayed transition occurred after the transition on the output terminal (12), a control signal on a line (78) is changed by incrementing a counter (74). This will increase the drive to a load (18).

Abstract: A method and system for screening semiconductor circuits is disclosed herein. A circuit 50, such as an SOI circuit, is provided. The circuit includes a plurality of transistors and is coupled to a supply voltage node V.sub.DD, a reference node V.sub.SS, and a substrate node V.sub.SUB. A supply voltage is applied to the supply node while a reference voltage is applied to the reference node and a test voltage is applied to the substrate node. The current I.sub.DD flowing to the supply and/or reference node is then measured. These steps are repeated for a plurality of test circuits to determine at least one performance and/or reliability criterion. The steps can then be repeated to screen other circuits by comparing the measured current to the reliability limit(s).

Abstract: A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal.

Abstract: A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).

Abstract: A full color projection system is disclosed herein. The projection system includes a means for generating a first light beam and also a means for generating a second light beam. These means may include either separate light sources 10a and 10b or a single light source 10 and a means for dividing the light source into the first and second light beams. In two examples, the means for dividing may include either a dichroic color wheel 40 or a color splitting prism 52. The first light beam will be modulated by a first spatial light modulator 30a and the second light beam will be modulated by a second spatial light modulator 30b. These spatial light modulators 30a and 30b are preferably, but not in necessarily digital micromirror devices.