Abstract: A compensation circuit 10 is disclosed herein. The circuit includes a control circuit 14 including a delay element 18 with a delay sensitive to at least one parameter which causes variations in delay and also comprises a compensated driver circuit 16. The compensated driver circuit 16 has a control input B coupled to the control circuit 14 and a signal input C coupled to an input circuit 12. The delay of an output signal OUT of the compensated driver circuit 16 is controlled in part by the control circuit 14 which modifies the delay of the output signal OUT in response to variation of the parameter. Other systems and methods and numerous variations are also disclosed.

Abstract: In one aspect, the present invention provides an air coil 20. The air coil 20 may be made from a strip of electrically conductive material 22 which has an insulating material overlying it. For example, the conductive material may comprise copper. The strip 22 is wound into a coil to perform a plurality of windings. The insulating material electrically insulates each of the winding from adjacent ones of the windings.

Abstract: A charge pump (10) uses Schottky diodes (12) coupled to clock signals (.phi..sub.1 and .phi..sub.2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16).

Abstract: A high voltage power transistor cell is developed that provides improved RDSon performance without sacrificing breakdown performance through utilization of trench based transistor technology. A source, drain and trench are formed within a substrate. A gate is formed or the surface over a spacing between the source and the trench. A drift region is formed around the trench. An isolation region may optionally be added allowing electrical isolation between the source and the substrate. The lateral current flow feature allows multiple high voltage power transistors, electrically isolated from one another, to exist on a single semiconductor chip. The drift region formed around the trench provides RESURF transistor characteristics without sacrificing die area.

Abstract: A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semiconductor and the substrate 12 may be silicon, quartz, gallium arsenide, glass, ceramic, metal or polyimide. A neutral (undoped) layer 16 of radiation sensitive material is formed over the doped layer 14. First and second source/drain regions 18 and 20 are formed in the neutral layer 16 and extend to a top portion of the doped layer 14. A gate region 22 is formed in a top portion of the neutral layer 16 between the first source/drain region 18 and second source/drain region 20 such that a channel region 24 is formed in the doped layer 14 beneath the gate region 22.

Abstract: In one aspect, the present invention provides an integrated inductor and capacitor 20 which can be used as the inductive portion of a resonant circuit and the energy accumulator for a identification system transponder. In a first embodiment, the integrated inductor and capacitor component 20 may include first and second strips of electrically conductive material 22 and 26, for example aluminum. The first and second strips 22 and 26 are wound in a coil 20 to form a plurality of windings. Each winding is electrically insulated from adjacent ones of the windings by insulators 24 and 28. The component can be bonded to a transponder chip.

Abstract: A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.

Abstract: The described embodiments of the present invention provide a trench etching technique having a high level of control over the sidewall profile of the trench and a high degree of selectivity to the etch mask. The described embodiments are for etching silicon and tungsten, but the invention is suitable for etching a wide variety of materials. A silicon etchant such as HBr, the combination of HBr/SF.sub.6, BCl.sub.3, SICl.sub.4 or other etchant is combined with a passivant such as carbon monoxide or nitrogen. The passivant gases include an interactive .pi. bonding system and/or paired electrons not involved in bonding. These passivant gases create a weak adductive bond to the dangling bonds or radicals generated during etching. The passivant gases also create a weak adductive bond to the sides of the trench being etched and are not removed due to the oblique angle of the sidewalls relative to the reactive ion flux vector corresponding to the trench etch.

Abstract: Channel stops for MIS infrared photodetector devices in Hg.sub.1-x Cd.sub.x Te by lattice damage (454) between and automatically aligned to MIS gates (408). Also, field plates and guard rings are automatically aligned to MIS gates.

Abstract: A method and system for screening semiconductor circuits is disclosed herein. A circuit 50, such as an SOI circuit, is provided. The circuit includes a plurality of transistors and is coupled to a supply voltage node V.sub.DD, a reference node V.sub.SS, and a substrate node V.sub.SUB. A supply voltage is applied to the supply node while a reference voltage is applied to the reference node and a test voltage is applied to the substrate node. The current I.sub.DD flowing to the supply and/or reference node is then measured. These steps are repeated for a plurality of test circuits to determine at least one performance and/or reliability criterion. The steps can then be repeated to screen other circuits by comparing the measured current to the reliability limit(s).

Abstract: A non-volatile memory cell 10 is disclosed herein. The cell is formed in a first semiconductor region 12 of a first conductivity type. A second semiconductor region 14 of a second conductivity type formed over the first semiconductor region 12. A third semiconductor region 16 of the first conductivity type formed over the second semiconductor region 14. In the preferred embodiment, the second and third regions 14 and 16 are well regions formed within the first region 12. Other regions such as epitaxially grown layers can also be used. First and second source/drain regions 18 and 20 are formed within the third semiconductor region 16. These second source/drain regions 18 and 20 are separated by a channel region 22. A floating gate 26 overlies at least a portion of the channel region 22 while a control gate 30 overlies the floating gate 26.

Abstract: A phase detector 10 is disclosed herein. A clock signal CLK (OR I), a marker signal MARK (or Q) and a data signal D are provided. The data signal may comprise a periodic clock signal. Sampler circuitry 50 receives the clock signal CLK, the marker signal MARK and the data signal D and generates a sampled clock signal and a sampled marker signal. Sign modifier circuitry 52 then receives the sampled clock signal and sampled marker signal and generates first and second command signals. Select circuitry 54 receiving these command signals selects a valid command signal based upon the data signal.

Abstract: A semiconductor controlled rectifier is disclosed herein. In a preferred embodiment, a first n-doped region 112 is formed in a p-doped semiconductor layer 126. A first n-well region 122 is formed within the first doped region 112. This well 122 extends through the region 112 and into the layer 126. A second n-doped region 114 is also formed in the layer 126. The second region 1114 is spaced from the first region 112. A second n-well 142 is formed in the layer 126 such that it partially overlaps the second region 114. A n-doped region 144 and a p-doped region 146 are each formed in the second n-well 142 and abut one another.

Abstract: A system and method for communicating between an identification reader 12 and a transponder unit 10 is disclosed herein. A first interrogation signal is transmitted from the reader 12. This first interrogation signal having a first read range. A first response signal is then received at the reader 12 after which a second interrogation signal is transmitted from the reader 12. The second interrogation signal has a second read range which is different than said first read range. The read range can be varied by varying either the amplitude or duration of the power level of the interrogation signal. A second response signal is then received at the reader 12. These consecutive responses are then compared determine a correct response signal which can be displayed.

Abstract: An improved method of affixing spheres 4 to a foil matrix 2 is described herein. First, a cell sandwich 32 is prepared. This cell sandwich 32 includes spheres 4 mounted on a foil matrix 2 which are disposed between upper and lower pressure pads 34 and 36. The cell sandwich 32 is then heated (e.g., to about 530.degree. C.). The spheres 4 are then affixed to the foil matrix 2 by directing the cell sandwich 32 through a roll press 48 which compresses the heated cell sandwich 32.

Abstract: An apparatus including an object 10 associated with a contactless, electronic identifier is disclosed herein. In one example, the object 10 is a trash bin. This object 10 is formed from a non-conductive material. A single-loop antenna 14 is disposed adjacent the object 10. An impedance transformer 18 which is matched to the single-loop antenna 14 is used to generate a desired inductance. A transponder 12 is also disposed near to and associated with the object 10. The transponder 12 is coupled to the antenna 14 through the impedance transformer 18.

Abstract: An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100); introducing a dopant of a first conductivity type into the substrate to form high-voltage tank regions (103); annealing the dopants (105); introducing dopants of the first conductivity type and a second conductivity type in a region in the high-voltage tank region (109); annealing the dopants of the first and the second conductivity type to form a second region within a third region, both within the high-voltage tank region, due to the different rates of diffusion of the dopants (110); and forming gate structures after the annealing of the dopants of the first and second conductivity types (122).

Abstract: The device hereof provides an integrated circuit resistor (34) comprising amorphous or noncrystalline semiconducting material. Further advantages can be gained in area by forming the noncrystalline semiconductor resistor in a non-planar fashion (i. e. with a vertical construction) wherein a first electrical contact is made to the resistor on its bottom surface and a second electrical contact is made to the resistor on its top surface.Other devices, systems and methods are also disclosed.

Abstract: An improved method of affixing spheres 4 to a conductive foil sheet 28 is described herein. A cell matrix is provided. The cell matrix includes a conductive foil matrix 2 with spheres 4 mounted therein. Each of the spheres 4 has an insulating layer 20 disposed on it. A portion of this insulating layer 20 is removed from each of the spheres 4 to expose a portion 22 of the spheres 4. A cell sandwich 32 is then formed between an upper pressure pad 34 and a lower pressure pad 36. The cell sandwich 32 includes the cell matrix 2/4 and a conductive foil 28. The cell sandwich 32 is then heated (preferably to between about 350.degree. and 450.degree. C.). The spheres 4 are then affixed to the conductive foil 28 by compressing the cell sandwich 32. In one embodiment, the compression takes place in a roll press 48.

Abstract: In one embodiment, a non-volatile memory cell structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region 21. A floating gate 13 is formed over and insulated from the channel region 21 and a control gate 14 is formed over and insulated from the floating gate 13. A lightly doped region 20 is formed in the channel 21 beneath the floating gate 13 and adjoining the source region 11. The lightly doped region 20 is spaced from the surface of said substrate 8. Other embodiments and processes are also disclosed.