Abstract: A method for forming a planar insulating layer over the surface of a semiconductor workpiece 8 which includes at least one low region 13 is discussed herein. The first step is to form a layer of blocking material 14 on the surface of the workpiece 8. A first material region 20 is then formed in the low region 13 and an insulating layer 21 is formed over the surface of the workpiece 8 including the first material region 20. The workpiece 8 is then heated in the presence of an active ambient such that the insulation layer 21 reflows and also so that the first material 20 region reacts with the active ambient to create an internal stress in said insulation layer 21. Other systems and methods are also disclosed.

Abstract: A lateral DMOS (LDMOS) transistor 10 is disclosed herein. In one embodiment, an n doped silicon layer 14 is provided and a field oxide region 24 is formed therein. A p doped D-well region 20 is formed in the silicon layer 14 and includes a p doped shallow, extension region 22 which extends from the D-well region 20 to a first side of the field oxide region 24. A first n doped source/drain region 16 is formed in the D-well region 20 and is spaced from the field oxide region 24. Also, a second n doped source/drain region 18 formed in the silicon layer 14 on a second side of the field oxide region 24. A gate region 26 is formed over the surface of the silicon layer 14 and over a portion of the first source/drain region 16, the D-well region 20, and a portion of the field oxide region 24.

Abstract: A system 20 for measuring the sheet resistance of a conductive layer on the top surface of a semiconductor wafer 22 is disclosed herein. In one embodiment, the system includes a chuck 30 electrically coupled to the backside surface of the wafer 22. The chuck 30 is capable of supporting the wafer 22 electrostatically. A signal source 40 provides an excitation signal to the wafer 22 and circuitry for monitoring an induced signal is provided. The sheet resistance on the top surface of the wafer 22 is determined from the measurements of the excitation and induced electrical signals. Other systems and methods are also disclosed.

Abstract: A semiconductor 110 device includes an array of like base cells wherein each base cell includes at least one source 132 and at least one drain 130 region formed in a semiconductor substrate. At least one gate 126 is formed over and insulated from a channel region 118 which separates the source 132 and drain 130 regions. An insulating layer 190 overlies the structure. A plurality of contacts are formed in the insulating layer in a plurality of substantially parallel, evenly spaced grid lines G1-G5. In addition, at least one additional contact 150 formed between two adjacent ones G2 and G3 of the substantially parallel grid lines is formed. A plurality of interconnect lines 142 and 144 are formed over the insulating layer such that each contact is connected to at least one of the interconnect lines. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.

Abstract: A method of forming a LDMOS transistor device 10 is disclosed herein. A semiconductor layer 14 is provided. The layer 14 may be an n-type RESURF region formed over a p-substrate 12. An insulating layer 24, such as a field oxide, is formed on the semiconductor layer 14. The insulating layer 24 is then patterned to expose source and drain windows. A D-well region 20 is then formed within the source window portion of the semiconductor layer. A sidewall region is formed adjacent a sidewall of the insulating layer around the source window. The source and drain regions 16 and 18 are then formed, for example by implanting arsenic or phosphorus ions. A gate electrode 26 is formed over a portion of the D-well region 20 between the source region 16 and the insulating layer 24. The gate electrode 26 is formed over a channel region within the D-well 20 between the source 16 and drain 18.

Abstract: A semiconductor controlled rectifier is disclosed herein. In a preferred embodiment, a first n-doped region 112 is formed in a p-doped semiconductor layer 126. A first n-well region 122 is formed within the first doped region 112. This well 122 extends through the region 112 and into the layer 126. A second n-doped region 114 is also formed in the layer 126. The second region 1114 is spaced from the first region 112. A second n-well 142 is formed in the layer 126 such that it partially overlaps the second region 114. A n-doped region 144 and a p-doped region 146 are each formed in the second n-well 142 and abut one another.

Abstract: A bolometer for detecting radiation in a spectral range is described herein. The bolometer includes an integrated circuit substrate 122 and a pixel body 120 spaced from the substrate 122 by at least one pillar 124. The pixel body 120 comprises an absorber material 132, such as titanium for example, for absorbing radiation in the spectral range, which may be 7 to 12 microns for example. The absorber material 132 heats the pixel body 120 to a temperature which is proportional to the absorbed radiation. An insulating material 134 is formed over the absorber material 132. In addition, a variable resistor material 136, possible amorphous silicon for example, with an electrical resistance corresponding to the temperature of the pixel body 120 is formed over said insulating layer 134. A current flows through the variable resistor material 136 substantially parallel to the integrated circuit substrate 122 for detection. Other systems and methods are also disclosed.

Abstract: A charge pump (10) uses Schottky diodes (12) coupled to clock signals (.phi..sub.1 and .phi..sub.2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16).

Abstract: An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor. The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor. Other buffers, palette devices, computer graphics systems and methods are also disclosed.

Abstract: A differential fuse circuit 10 is disclosed herein. A first fuse 12 and a second fuse 14 are coupled to a supply potential V.sub.DD (e.g., five volts). Circuitry 16 and 18 for blowing the two fuses 12 and 14 is also provided. A current mirror 46 including a first leg and a second leg is also provided. The current mirror 46 is designed so that a current through the first leg will induce a current in the second leg. The first leg is coupled between the first fuse 12 and a reference potential V.sub.SS and the second leg is coupled between the second fuse 14 and the reference potential V.sub.SS. An output node 56 is provided between the second fuse 14 and the second leg of the current mirror 46. A differential sense circuit 24 may also be included between the fuses 12 and 14 and the current mirror 46.

Abstract: An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100); introducing a dopant of a first conductivity type into the substrate to form high-voltage tank regions ( 103); annealing the dopants (105); introducing dopants of the first conductivity type and a second conductivity type in a region in the high-voltage tank region (109); annealing the dopants of the first and the second conductivity type to form a second region within a third region, both within the high-voltage tank region, due to the different rates of diffusion of the dopants (110); and forming gate structures after the annealing of the dopants of the first and second conductivity types (122).

Abstract: A transistor device 10 formed in a semiconductor layer 12 is disclosed herein. A first source/drain region 14 is formed in the semiconductor layer 12. A second source/drain region 16 is also formed in the semiconductor layer 12 and is spaced from the first source/drain region 14 by a channel region 18. The second source/drain region 16 includes (1) a lightly doped portion 16b adjacent the channel region 18 and abutting the top surface, (2) a main portion 16a abutting the top surface and spaced from the channel region 18 by the lightly doped portion 16b, and (3) a deep portion 16c formed within the layer 12 and spaced from the top surface by the lightly doped portion 16b and the main portion 16a. A gate electrode 20 is formed over at least a portion of the channel region 18 and insulated therefrom.

Abstract: A method of forming an integrated circuit comprising forming a plurality of modules on a chip. In addition, a plurality of conductive bond regions are formed adjacent the chip. Further, selected bond regions are coupled to selected modules such that a subset of the plurality of modules may be accessed by the selected bond regions.

Abstract: A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD.

Abstract: A method and system for screening semiconductor circuits is disclosed herein. A circuit 50, such as an SOI circuit, is provided. The circuit includes a plurality of transistors and is coupled to a supply voltage node V.sub.DD, a reference node V.sub.SS, and a substrate node V.sub.SUB. A supply voltage is applied to the supply node while a reference voltage is applied to the reference node and a test voltage is applied to the substrate node. The current I.sub.DD flowing to the supply and/or reference node is then measured. These steps are repeated for a plurality of test circuits to determine at least one performance and/or reliability criterion. The steps can then be repeated to screen other circuits by comparing the measured current to the reliability limit(s).

Abstract: A power MOSFET device formed in a face of a semiconductor layer of a first conductivity type is provided. A first, second and third source region of a second conductivity type are formed in the face of the semiconductor layer within a moat and adjacent to its edges. A source conductor is insulatively disposed adjacent the face of the semiconductor layer and contacts the first, second and third source regions at a plurality of locations. A first and second drain region of a second conductivity type is also formed in the face of the semiconductor layer disposed spaced from and between the first and second source regions and the second and third source regions, respectively. A drain conductor is insulatively disposed adjacent the face of the semiconductor layer and contacts the first and second drain regions at a plurality of locations.

Abstract: An integrated circuit is designed by determined the devices comprising the integrated circuit and determining the desired parameters for each device. A flow of process steps is determined and the 1-D and 2-D simulations are performed on the process flow. The process steps are modified until the simulations determine that the desired parameters are met.

Abstract: A method for patterning an integrated circuit workpiece comprises depositing a layer of non-photoactive material on the wafer. A reagent is deposited onto the entire surface of the material. A pattern is then created by exposing the surface with an energy source which produces a reaction within the reagent and/or between the reagent and the resin. The unreacted reagent is then removed by either physical or chemical means. Finally, the unexposed material is removed by means of an etch.

Abstract: An improved metallized structure (10) is formed from a copper seed layer (46) and a copper structure (48). Semiconductor devices to be connected (16-18) are covered by a conductive barrier layer (20). An oxide layer (28) is then deposited over the barrier layer (20) and patterned using standard photolithographic techniques and an anisotropic plasma etch. Vertical sidewalls (36-38) are formed by the etch and an HF deglaze. A seed layer (44-46) is then sputtered onto a photoresist layer (30) and the exposed barrier layer (20). After stripping the photoresist (30) and the seed layer (44) thereon, the copper structure (48) is electroplated over the remaining seed layer (46). The structure (48) thus formed has approximately vertical sidewalls (24-26) for improved contact with subsequent layers.

Abstract: A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100). It is possible to form the element areas according to designs, and it is also possible to flatten the surface without wire cutting in the conductive layer.