Abstract: A static memory cell comprises a first PMOS transistor including a drain 319, a channel 344, a source 317, and a lightly doped drain 360 and a first NMOS transistor including a source 323, a channel 346, and a drain 321. A first gate 334 insulatively overlies the channel 344 and the lightly doped drain region 360 of the first PMOS transistor as well as the channel 346 of the first NMOS transistor. The memory cell also includes a second PMOS transistor which in turn includes a source 327, a channel 362, a source 325, and a lightly doped drain 364 and a second NMOS transistor which includes a source 323, a channel 368, and a drain 329. A second gate 338 insulatively overlies the channel 362 and the lightly doped drain region 364 of the second PMOS transistor and the channel 368 of the second NMOS transistor.

Abstract: A nonvolatile memory array has two or more stacked layers of memory cells (10). The bottom layer may comprise a planar, X-cell, or buried N++ FAMOS transistor array and the top layer preferably comprises a planar transistor array. An epitaxial silicon layer (36) provides the substrate for the second layer. The stacked layer structure allows a two-fold increase in memory density without scaling the device sizes.

Abstract: A photolithographic mask or a directly written wafer has a pattern formed on a substrate 320. A grid pattern 316 and a layer of resist material 322 are formed on the substrate 320. The grid pattern 316 may be either above or beneath the resist material 320. The grid pattern 316 is scanned, by an e-beam or optical beam for example, without substantially reacting the resist layer 320 to obtain information on the location of the grid pattern 316. Portions of the resist material 320 are then exposed to form a device pattern. The device pattern is determined in part from the information and is also formed over the grid pattern 316. Other systems and methods are also disclosed.

Abstract: A DRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: A combination dynamic random access memory (DRAM) and static random access memory (SRAM) (150) array, includes a plurality of DRAM sense amplifiers (82, 84), each coupled to at least one DRAM bitline (86), with a plurality of DRAM memory cells selectively coupled to each of the bitlines (86). The sense amplifiers (82, 84) are organized into groups, with each group of sense amplifiers (82, 84), selectively coupled to respective true and complement I/O lines (102, 104). For each pair of the true and complement I/O lines (102, 104), an SRAM latch (150) is coupled to the pair.

Abstract: A bolometer for detecting radiation in a spectral range is described herein. The bolometer includes an integrated circuit substrate 122 and a pixel body 120 spaced from the substrate 122 by at least one pillar 124. The pixel body 120 comprises an absorber material 132, such as titanium for example, for absorbing radiation in the spectral range, which may be 7 to 12 microns for example. The absorber material 132 heats the pixel body 120 to a temperature which is proportional to the absorbed radiation. An insulating material 134 is formed over the absorber material 132. In addition, a variable resistor material 136, possible amorphous silicon for example, with an electrical resistance corresponding to the temperature of the pixel body 120 is formed over said insulating layer 134. A current flows through the variable resistor material 136 substantially parallel to the integrated circuit substrate 122 for detection. Other systems and methods are also disclosed.

Abstract: A GaAs MESFET employs an etch stop layer of Ga.sub.0.99 In.sub.0.01 As over the channel region.

Abstract: The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor.

Abstract: The invention relates to an integrated transistor circuit comprising a transistor (Q1) of which the collector is connected to an input of a circuit (S) and between the base and collector of which an antisaturation diode (D1) is connected. According to the invention a further current branch is provided between the base and the emitter and includes a series circuit of a diode (D2) and a resistor (R1). As a result, a leakage current flowing in reverse direction into the antisaturation diode (D1) flows via the diode (D2) and the resistor (R1) and not via the emitter-base path of the transistor (Q1) and consequently amplification of the leakage current is prevented.

Abstract: A method of forming a semiconductor gate array structure on a semiconductor substrate comprises the steps of forming a plurality of moat regions 12 and 14 where each of the moat regions 12 and 14 includes a channel region 22 and 28 and an insulating layer formed over the channel region 22 and 28. The moat regions separated by an insulating region 16. A plurality of gates 30 are formed wherein each of said gates 30 includes a first portion 30a over one of said channel regions 22, a second portion 30b over a channel region 28 adjacent to said one of said channel regions, and a third portion 30c over the insulating region 116 between said one of said channel regions. The gates 30 are formed such that each channel region is beneath one gate. The third portion 30a of a selected number of the gates is then etched to form the desired gate configuration.

Abstract: A multi-switch processing methodology and a multi-channel time-division plasma chopping device (10) for in-situ plasma-assisted semiconductor wafer processing associated with a plasma and/or photochemical processing equipment. The device (10) comprises a main transfer channel (72) associated with the processing reactor for transferring process gas and activated plasma mixtures into the reactor. A plurality of gas discharge channels (18, 22, 26, and 30) associate with the main transfer channel (72) for independently directing various gases and activated plasma combinations to main transfer channel (72). Process excitation sources (16, 20, 24 and 28) associate with at least one of said gas discharge or activation channels to independently and selectively activate process gases and to control gas activation and flow from the discharge channels to the main transfer channel (72).

Abstract: An electrically-erasable and programmable read-only memory cell includes a gate insulator layer formed on the face of a semiconductor layer having a first conductivity type. A conductive floating gate is formed on the gate insulator layer and has first and second portions with a gap substantially laterally separating the first and second portions. An interlevel insulator layer is formed on exposed faces of the floating gate. A conductive control gate is formed on the interlevel insulator layer in the gap and to be capacitively coupled to the floating gate. A source region and a drain region of a second conductivity type are formed beside opposite exterior lateral margins of the floating gate. The EEPROM cell of the invention avoids channel length alignment problems found in prior art EEPROM cells.

Abstract: An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor. The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor. Other buffers, palette devices, computer graphics systems and methods are also disclosed.

Abstract: According to the invention, a semiconductor device is provided at the face of a substrate. A layer of insulator is formed adjacent the face of substrate, layer of insulator having a window disposed therethrough. A region of epitaxially semiconductor is disposed in window informs an interface with adjacent portions of layer of insulator. A seal is provided at interface of the region of epitaxial semiconductor and the layer of insulator.

Abstract: In one embodiment, a non-volatile memory cell structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region 21. A floating gate 13 is formed over and insulated from the channel region 21 and a control gate 14 is formed over and insulated from the floating gate 13. A lightly doped region 20 is formed in the channel 21 beneath the floating gate 13 and adjoining the source region 11. The lightly doped region 20 is spaced from the surface of said substrate 8. Other embodiments and processes are also disclosed.

Abstract: A modeling system 10 comprises a central processing unit 12 coupled to an arithmetic logic unit 16. A device testing system 18 is used to imperically analyze the operational characteristics of a transistor to be modeled by the system 10. A set of parameter values are stored in a memory circuit 14 coupled to central processing unit 12. An input and display system 20 is used to interact with the central processing unit 12. The central processing unit 12 uses the arithmetic logic unit 16 to calculate an objective function which comprises a sum of a plurality of two types of terms. The first term within the objective function utilizes relative weighting with respect to the values of the remaining terms while the second type of term utilizes absolute weighting with respect to the remaining terms. Both types of terms are normalized such that they are of substantially equal significance during the calculation of the objective function.

Abstract: A method of forming doped wells 24 and 30 in a semiconductor layer is disclosed herein. In a preferred embodiment, an oxide layer 16 is formed on the surface of a silicon layer 14. A nitride layer 18 is then formed on the oxide layer 16 and is patterned and etched to define a first well region 24. The first well region 24 is then doped, for example with phosphorus or boron. A resist layer 26 is formed over the first well region 24 and over a portion of the nitride layer 18 after which a portion of the nitride layer 18 not beneath the resist layer 26 is removed to expose a second well region 30. The second well region 30 is then doped. After the remaining portion the resist layer 26 is removed, an oxide layer 32 is formed over the first 24 and second 30 well regions while the surface 38 over the region 36 separating the well regions is left bare. The semiconductor wafer 10 is then heated in a nitridizing environment (e.g.

Abstract: A multi-point non-invasive, real-time pyrometry-based temperature sensor (200) for simultaneously sensing semiconductor wafer (22) temperature and compensating for wafer emissivity effects. The pyrometer (200) measures the radiant energy that a heated semiconductor wafer (22) emits and coherent beams of light (224) that the semiconductor wafer (22) reflects. As a result, the sensor (200) generates accurate, high-resolution multi-point measurements of semiconductor wafer (22) temperature during a device fabrication process. The pyrometer (200) includes an infrared laser source (202) that directs coherent light beam (203) into beam splitter (204). From the beam splitter (204), the coherent light beam (203) is split into numerous incident coherent beams (210). Beams (210) travel via optical fiber bundles (218) to the surface of semiconductor wafer (22) within the fabrication reactor (80). Each optical fiber bundle (218) collects reflected coherent light beam and radiant energy from wafer (22).

Abstract: A semiconductor wafer (32) is patterned to have gettering areas (36-38) selectively positioned proximate devices (44-46) which require gettering. The areas (36-38) comprise germanium-doped silicon having a germanium concentration of approximately 1.5%-2.0%. The germanium creates a lattice mismatch between the substrate (32) and an epitaxial layer (34) which is sufficient to produce defects capable of gettering contaminants. The gettering areas (36-38) may be formed by selective deposition, selective etching, ion-implantation or selective diffusion techniques.