Abstract: A driving method and a transreflective display apparatus are provided herein. In the driving method, a plurality of voltage-to-transparency curves are provided. An ambient light intensity of the display apparatus is detected for determining a display mode, wherein the display mode is either a transmissive mode or a reflective mode. Next, one of the voltage-to-transparency curves is selected according to the display mode and the ambient light intensity for driving the display apparatus. Therefore, by referring a proper voltage-to-transparency curve to drive the display apparatus, the display quality of the display apparatus can be enhanced.

Abstract: The subject is to provide a liquid crystal composition that satisfies at least one characteristic of characteristics such as a high maximum temperature of a nematic phase, a low minimum temperature of a nematic phase, a small viscosity, a suitable optical anisotropy, a negatively large dielectric anisotropy, a large specific resistance, a high stability to ultraviolet light and a high stability to heat, or that is suitably balanced regarding two characteristics thereof. The subject is to provide an AM device that has a short response time, a large voltage holding ratio, a large contrast ratio, a long service life and so forth.

Abstract: A network transmitting apparatus and a power saving method thereof are provided. The network transmitting apparatus includes a chip, a transformer, and a power regulating unit. The chip includes a detecting and controlling unit, an analog circuit, and a digital circuit. The detecting and controlling unit receives a received signal and detects the received signal and a state of the chip to generate a first control signal. The transformer has a first side coupled to the chip and a second side. The power regulating unit coupled to the detecting and controlling unit and a center tap of the first side of the transformer is used for receiving a voltage, generating a first regulated voltage according to the first control signal, and connecting the first regulated voltage to the center tap of the first side of the transformer, the analog circuit, and the digital circuit.

Abstract: A fan controlling circuit is provided. The fan controlling circuit includes an integral unit, an operational amplifier, and an output unit. The integral unit transforms pulse width modulation signals to voltages, and then the output unit outputs one of the pulse width modulation signals having a higher operation frequency according to the comparison result between the voltages. As the fan controlling circuit may be constituted with discrete elements and use a same voltage source as fans, the design cost and complexity are reduced.

Abstract: A sample introduction method for reducing carry-over is provided. After a sample introduction device in a total volume injection method draws a proper amount of a sample solution from a sample container and further draws a solution with the same composition as a mobile phase solution with a needle 24, the needle 24 is inserted into an injection port 25. When flow paths are switched to communicate a liquid feeder, a sample loop 23, the needle 24, the injection port 25, and a separation/detection section, the solution with the same composition as the mobile phase solution is forced into a gap between the injection port 25 and the needle 24. Therefore, the samples squeezed out of a tip section of the needle 24 during the switching of the flow paths are prevented from being forced into the gap between the needle 24 and the injection port 25.

Abstract: A process for preparing a polyether ether ketone. Sodium carbonate is used alone as the condensation agent, and 4,4?-difluorodibenzophenone, p-benzenediol and biphenyldiol are subjected to polymerizing. After the corresponding prepolymer is obtained, the reaction temperature is elevated and p-benzenediol is further added as a chain extender to react for a period of time to produce high-viscosity polyether ether ketone.

Abstract: A paper tray of printer is provided, which includes a paper tray body, a slide shaft, a first pick arm, a second pick arm and a paper width guide. The first pick arm is fixed on the slide shaft, and the second pick arm is slidely disposed on the slide shaft. The paper width guide is disposed on the paper tray body and is connected to the second pick arm through a linkage device to drive the second pick arm, so that a position of the second pick arm varies along with a position of the paper width guide. Accordingly, an interval between the first pick arm and the second pick arm can be varied along with a size of a paper, so as to avoid paper skew when the paper is fed.

Abstract: The present invention relates to a comprehensive test bed for vehicle body, which comprises an vehicle body static strength testing apparatus, an vehicle body air tightness testing apparatus, an vehicle coupler strength testing apparatus and an vehicle body mode testing apparatus, wherein the tested vehicle body is provided with a strain foil and a displacement sensor; and the strain foil and the displacement sensor are connected with a data acquisition system. The comprehensive test bed for the vehicle body can perform an vehicle body static strength test on various rail passenger vehicles, an vehicle body steel structure vibration mode test, an vehicle body partial assembly vibration mode test and an vehicle body air tightness test, and can realize strength tests on partial key components of the vehicle body (a transition vehicle coupler, a return vehicle coupler, an vehicle body chassis cross beam, a hoisting structure, an end structure, and the like).

Abstract: A flash memory storage system and a data writing method thereof are provided. The flash memory storage system includes a controller, a connector, a cache memory, a SLC NAND flash memory and a MLC NAND flash memory. When the controller receives data to be written into the MLC NAND flash memory from a host system, the data is temporarily stored in the cache memory first and then is written into the MLC NAND flash memory from the cache memory. And, the controller may backup the data stored in the cache memory to the SLC NAND flash memory. Accordingly, it is possible to reduce a response time for a flush command, thereby improving a performance of the flash memory storage system.

Abstract: An output buffer including a differential amplifier, a first and a second output stage, and a first and a second control stage is provided. The differential amplifier receives an input and a feedback signal and accordingly adjusts the level of the first and second control signals. The first control stage determines to provide a first current to an output terminal of the output buffer according to the level of the first and second control signals. The first control stage is biased under a high voltage and outputs one of the first control signal and the high voltage. The second control stage is biased under the low voltage and outputs one of the second control signal and the low voltage. The second output stage determines to provide a second current to the output terminal of the output buffer according to the signal generated by the first and second control stages.

Abstract: By simultaneously administering a chemical using a nuclear species releasing a single photon (a first chemical) and another chemical using a nuclear species releasing a positron to a subject, the cumulative distributions of the respective chemicals are monitored. A plural number of ?-ray detectors, which are circularly located, and a collimator covering some of the ?-ray detectors and rotates along the front face of the ?-ray detectors are provided. Also, an energy discriminating means for discriminating signals having a single photon ?-ray energy (first signals) from signals having annihilation ?-ray energy (second signals) among all of the signals detected by the detectors is provided. Further, the cumulative position of the first chemical is specified based on the signals corresponding to the ?-ray detectors covered with the rotating collimator from the first signals.

Abstract: A server chassis layout structure includes a chassis body, a partition plate, and a power backplane module. The chassis body includes a bottom plate, first and second top plates, and two side plates. The first and second top plates form a first opening therebetween. The side plates are mounted between the bottom and top plates. The partition plate includes at least one retaining portion and is perpendicularly fixed to the bottom plate below the first opening. The partition plate divides the chassis body into first and second sections. The power backplane module includes at least one lock portion and is vertically inserted into the chassis body via the first opening. The lock portion interferes with the retaining portion so as to assemble the power backplane module into the chassis body above the partition plate, and both the power backplane and the partition plate are exposed via the first opening.

Abstract: A fine symbol timing synchronization method and apparatus in an orthogonal frequency-division multiplexing (OFDM) system are provided. The fine symbol timing synchronization method finds a path with a minimum mean square error (MMSE) as a first path among a plurality of paths, and a formula of the mean square error (MSE) used by the method is a simplified formula of the original MSE formula with low calculation complexity. Therefore, the time required by the fine symbol timing synchronization method is short, and a correct first path can be found, so as to lock a starting position of a fast Fourier transform (FFT) window on a starting position of a symbol signal of the correct first path.

Abstract: A flash memory storage system including a flash memory chip, a connector, and a flash memory controller is provided. The flash memory controller configures a plurality of logical addresses and maps the logical addresses to a part of the physical addresses in the flash memory chip, and a host system uses a file system to access the logical addresses. Besides, the flash memory controller identifies a deleted logical address among the logical addresses and marks data in the physical address mapped to the deleted logical address as invalid data.

Abstract: A data backup method for backing up data temporarily stored in a cache memory of a flash memory storage device is provided, where the flash memory storage device has a plurality of physical units. The data backup method includes logically grouping a portion of the physical units into a data area and a cache area. The data backup method also includes determining whether a trigger signal is received; and when the trigger signal is received, copying the data temporarily stored in the cache memory into the cache area. Accordingly, the data backup method can quickly write the data temporarily stored in the cache memory into the physical units, thereby preventing a time out problem which may occur in the flash memory storage device.

Abstract: A strain balanced active-region design is disclosed for optoelectronic devices such as light-emitting diodes (LEDs) and laser diodes (LDs) for better device performance. Lying below the active-region, a lattice-constant tailored strain-balancing layer provides lattice template for the active-region, enabling balanced strain within the active-region for the purposes of 1) growing thick, multiple-layer active-region with reduced defects, or 2) engineering polarization fields within the active-region for enhanced performance. The strain-balancing layer in general enlarges active-region design and growth windows. In some embodiments of the present invention, the strain-balancing layer is made of quaternary InxAlyGa1-x-yN (0?x?1, 0?y?1, x+y?1), whose lattice-constant is tailored to exert opposite strains in adjoining layers within the active-region. A relaxation-enhancement layer can be provided beneath the strain-balancing layer for enhancing the relaxation of the strain-balancing layer.

Abstract: A block management method for managing blocks of a flash memory storage device is provided. The flash memory storage device includes a flash memory controller. The block management method includes the following steps. At least a part of the blocks is grouped into a first partition and a second partition. Whether an authentication code exists is determined. When the authentication code exists, the blocks belonging to the first partition are provided for a host system to access, so the host system displays the first partition and hides the second partition. An authentication information is received from the host system. Whether the authentication information and the authentication code are identical is authenticated. When the authentication information and the authentication code are identical, the blocks belonging to the second partition are provided for the host system to access, so the host system displays the second partition and hides the first partition.