Abstract: A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer.

Abstract: In the production process of the present invention for high purity polycrystal silicon, using a vertical reactor having a silicon chloride gas-feeding nozzle and a reducing agent gas-feeding nozzle which are disposed at an upper part and a waste gas discharge pipe, a silicon chloride gas and a reducing agent gas are fed into the reactor to form polycrystal silicon at a tip part of the silicon chloride gas-feeding nozzle by the reaction of the silicon chloride gas with the reducing agent gas, and the polycrystal silicon is allowed to grow from the tip part of the silicon chloride gas-feeding nozzle toward a lower part thereof.

Abstract: A rail device and a server are provided. The server includes a rack, at least one chassis, and a rail device. The rail device is disposed on the chassis and the rack to move the chassis between a first position and a second position relative to the rack. The rail device includes a first rail, a second rail, a bracket, and a first latch. The first rail is installed on the rack, the second rail is installed in the chassis, the bracket is slidably coupled to the first rail and the second rail, and the first latch is disposed on the bracket. When the chassis moves away from the first position, the first latch locks the bracket and the chassis together, so that the chassis pushes the bracket forward.

Abstract: An electrode of an electrochemical cell and a method for fabricating the same is provided. The electrode is prepared by depositing ionomers to the catalyst layer of an electronic conductive layer, e.g. catalysts-coated carbon cloths. The ionomers are controllably deposited into the catalyst layer by applying a voltage. As a result, ionic conduction is enhanced and the reaction area of the three-phase-boundary region is increased.

Abstract: An image processing method including the following steps is provided. First, a two-dimensional original image is received. Next, a plurality of depth values corresponding to the two-dimensional original image are received. Afterwards, a two-dimensional shifting image is obtained according to the depth values and a standard value. A plurality of shifting values exist between the two-dimensional shifting image and the two-dimensional original image, and the shifting values are determined by a plurality of differences between the depth values and the standard value. Thereafter, a three-dimensional image is produced according to the two-dimensional original image and the two-dimensional shifting image.

Abstract: An electrical interconnecting structure suitable for a circuit board is provided. The electrical interconnecting structure includes a core, an ultra fine pattern, and a patterned conductive layer. The core has a surface, and the ultra fine pattern is inlaid in the surface of the core. The patterned conductive layer is disposed on the surface of the core and is partially connected to the ultra fine pattern. Since the ultra fine pattern of the electrical interconnecting structure is inlaid in the surface of the core and is partially connected to the patterned conductive layer located on the surface of the core.

Abstract: A touch apparatus including a touch capacitor and a touch control unit is provided. The touch control unit includes a signal sampling and saving unit, a switch unit, and a signal processing unit. The signal sampling and saving unit samples and saves a voltage on the touch capacitor during enable periods of a sample signal and a charge reset signal, so as to generate a touch voltage and a reset voltage respectively, and further generate an average voltage of the touch voltage and the reset voltage according to an equalization signal. The switch unit receives and transmits the touch voltage, the reset voltage, and the average voltage according to a first control signal. The signal processing unit couples the touch voltage, the reset voltage, the average voltage, and a common voltage according to a second control signal, so as to generate a first coupling voltage and a second coupling voltage.

Abstract: A data reading method for a flash memory module is provided. The method includes applying a bit-data-read voltage to get read data from memory cells of the flash memory module. The method also includes setting a minus-adjustment-bit-data-read voltage and a plus-adjustment-bit-data-read voltage corresponding to the bit-data-read voltage based on an error-distribution estimated value and applying the minus-adjustment-bit-data-read voltage and the plus-adjustment-bit-data-read voltage to obtain soft values corresponding to the read data from the memory cells. The method further includes calculating a soft-information estimated value corresponding to each bit of the read data according to the soft-values. Accordingly, the method can effectively obtain soft information.

Abstract: A data access method for accessing a non-volatile memory module is provided. The data access method includes configuring a plurality of logical addresses and grouping the logical addresses into logical blocks to map to the physical blocks of the non-volatile memory module, and a host system formats the logical addresses into one partition by using a file system and the partition stores at least one file and a file description block corresponding to the file. The data access method further includes searching an end mark corresponding to entry values of the file description block, setting logical addresses storing the end mark as default pattern addresses, and setting values stored in the logical addresses as default values corresponding to the default pattern addresses. Accordingly, the data access method can divide one partition into a write protect area and a writable area by updating data stored in the default pattern addresses.

Abstract: A three-dimensional distance woven fabric including two outer fabrics and a plurality of inter-yarns connected with the outer fabrics, wherein a gap distance between the outer fabrics is greater than 20 centimeters A method for weaving the aforesaid three-dimensional distance woven fabric is also provided.

Abstract: The present invention relates to a remote controller for an aircraft model, which includes a body, a mode selection switch, and a signal acquisition unit. The body is adapted to be held in a first direction and a second direction. The mode selection switch may be configured to issue a mode selection signal. The signal acquisition unit acquires the manipulation signals manipulated by the first joystick and the second joystick in the remote controller, and processes the manipulation signals according to the mode selection signal, so as to enable the remote controller to operate respectively in the first manipulation mode and the second manipulation mode. The remote controller of the present invention merely switches the electric signals for switching between the manipulation modes without modifying the mechanical structure, thereby simplifying the switching operations.

Abstract: A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.

Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one dielectric layer, at least one embedded capacitor, and at least one metal layer. The core circuit board has at least one wiring layer, and the core circuit board has at least one conductive through hole connected to the wiring layer. At least one dielectric layer covers the wiring layer, and the dielectric layer has at least one conductive through hole. At least one embedded capacitor is embedded in the dielectric layer. At least one metal layer covers the dielectric layer and connected to the embedded capacitor, wherein the metal layer is connected to the wiring layer through the conductive through hole.

Abstract: A method of fabricating a pixel structure of a thin film transistor liquid crystal display is provided. A transparent conductive layer and a first metallic layer are sequentially formed over a substrate. The first metallic layer and the transparent conductive layer are patterned to form a gate pattern and a pixel electrode pattern. A gate insulating layer and a semiconductor layer are sequentially formed over the substrate. A patterning process is performed to remove the first metallic layer in the pixel electrode pattern while remaining the gate insulating layer and the semiconductor layer over the gate pattern. A second metallic layer is formed over the substrate. The second metallic layer is patterned to form a source/drain pattern over the semiconductor layer. A passivation layer is formed over the substrate and then the passivation layer is patterned to expose the transparent conductive layer in the pixel electrode pattern.

Abstract: A limiting switch suitable for a testing device is provided. The testing device includes a fixed frame and a clamping element pivoted to each other. The limiting switch includes a first rod, a second rod, a first switching element and a second switching element. The first and second rods are fixed to the clamping element. The first and second switching elements are pivotally connected to the fixed frame. When the clamping element is pivoted along a first direction, the second rod pushes the second switching element to pivot and the first rod is moved to contact with the first switching element. When the clamping element is pivoted along a second direction opposite to the first direction, the first rod pushes the first switching element to pivot and the second rod is moved to contact with the second switching element.

Abstract: A source driver with low consumption and the driving method thereof are provided herein. The source driver includes an output buffer with a first input terminal receiving a pixel signal, a second input terminal, and an output terminal coupled to the second input terminal and a display panel. The source driver also includes a pre-charge circuit pre-charges a first terminal of the display panel to a first preset voltage or a second preset voltage for a pre-charge period according to a polarity of a common voltage coupled to the display panel. The second preset voltage is smaller than the first preset voltage. The output buffer is inactivated during the pre-charge period and activated for a preset period after the pre-charge period. Therefore, the present invention reduces power consumption of the source driver.

Abstract: A backlight controller, a display device using the same and a method for controlling a backlight module are provided. The backlight controller includes a temporal weighting module and a dimming controlling module. The temporal weighting module calculates a weight sum of a first backlight luminance provided in a current frame and a target backlight luminance to serve as an adjusted backlight luminance. The target backlight luminance is obtained according to an image content of the current frame. The dimming controlling module increases or decreases the adjusted backlight luminance by a step value according to the target backlight luminance and generates a second backlight luminance provided in a next frame. Therefore, a backlight luminance of the backlight module not only can be smoothly adjusted to the target backlight luminance at high speed for avoiding backlight flicker, but also can be adaptive to image content for saving electric power consumption.

Abstract: A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.

Abstract: A source driver, a display device and a driving method of the source driver are disclosed. The source driver adapted to a display panel includes a plurality of driving channels, wherein the display panel includes N pixel cells on each of a plurality of scan lines. The 1st driving channel to the Nth driving channel respectively drive the N pixel cells on a first scan line of the scan lines during a first scan period and the 2nd driving channel to the (N+1)th driving channel respectively drive the N pixel cells on a second scan line of the scan lines during a second scan period. When polarity inversion is performed on the display panel, each driving channel is responsible for outputting a data driving voltage with a certain polarity to the corresponding pixel cell during different scan periods. Therefore, the power consumption of the source driver can be decreased.