Abstract: A communications system includes a single transmitter and a large number of individual receivers. The transmitter broadcasts a signal over a medium a continuous stream of digitally coded text items, each carrying information as to one or more subjects described by an index term. Each receiver includes a demodulator for continuously receiving the broadcast signal, a profile storage tailorable by each user individually to contain a list of desired index terms, means for selecting only those items having index terms matching those in the profile storage, and a memory for storing the selected items. The user can activate the receiver to play back items in the memory and to choose among the stored items. The items chosen for playback are converted from digital text to a synthesized voice, which is sent as an audio signal to the user.

Abstract: A circuit to drive a brushless motor which consumes less power because it uses pulse width modulation. The invention has at least two loops; one loop to control the switching of transistors in a push-pull configuration drives current in the different coils of the motor when those transistors connected to ground are driven in a linear, rather than a saturated, mode. This loop also incorporates a soft switching waveform shaping circuit which slowly switches the phase current so that the electromagnetic noise of the motor does not enter the magnetic head on the disk. The other loop actually controls the speed of the motor based on the linear mode of the transistors.

Abstract: An electronics systems having variable interconnections among major components is tested by dynamically identifying the locations and types of all system components at the time the test is to be performed, for building a global model describing the interconnections among these components. Specific tests appropriate for this model are then dynamically generated and executed. Data on the components themselves identifies them. The tests employ boundary-scanning techniques to locate failing drivers, receivers, and bidirectional driver/receivers, as well as open and shorted interconnections.

Abstract: A communications system has a single transmitter and a large number of portable receivers. The transmitter broadcasts a continuous stream of coded text messages, each addressed to a particular user or group of users. Each receiver demodulates all the messages, compares their addresses with a list of addresses in the receiver, and stores only those messages having one of the proper addresses. The user can activate the receiver to play back messages in the memory, and to choose among the stored messages. The messages selected for playback are converted from digital text to a synthesized voice, sent as an audio signal to the user.

Abstract: Each item a system or order group carries a label having, in addition to a predetermined primary code denoting its item type, another, secondary, code representing a random identifier for that individual item. When a system or order group is to be packaged, a worker selects each item according to a list, scans its label, and physically places the item with the order group. The predetermined primary and random secondary codes are compared with those of previous items in the same order group. A complete match with the codes of another item in the same group causes the item to be rejected.

Abstract: A communications system has a single transmitter and a large number of portable receivers. The transmitter broadcasts a continuous stream of coded text messages, each addressed to a particular user or group of users. Each receiver demodulates all the messages, compares their addresses with a list of addresses in the receiver, and stores only those messages having one of the proper addresses. The user can activate the receiver to play back messages in the memory, and to choose among the stored messages. The messages selected for playback are converted from digital text to a synthesized voice, sent as an audio signal to the user.

Abstract: An information processing network includes multiple processing devices, a main storage memory, and an interface coupling the processing devices to the main storage memory. All processing devices contend for control of the interface on an equal basis, subject to a dynamically shifting sequence of priority rankings, invoked to resolve contentions for the interface or for one of a plurality of hardware class locks. The class locks are uniquely associated with different capabilities or classes of data operations, which reduces the number of contentions and allows multiple operations to proceed simultaneously. Arbitration logic encompassing all of the processing devices is duplicated in each of the processing devices, and kept coherent through an interconnection of multiple data buses. One bus is associated with each processing device, receives the output of the associated processing device and provides the output to each of the other processing devices.

Abstract: An N-channel and P-channel MOSFET include counterdoping of a threshold voltage (V.sub.T) ion implant for reducing substrate sensitivity and source/drain junction capacitance. An arsenic (As) compensated boron (B) implant is provided in the N-channel MOSFET. A boron (B) compensated arsenic (As) implant is provided in the P-channel MOSFET.

Abstract: A computer converts a description of an analog circuit to a physical representation in terms of devices on a personalizable chip. The devices are placed and wired automatically for fabrication of the chip. Descriptions of resistors in the circuit are expanded by wiring multiple contacts of one or more actual resistor devices on the chip. The chip uses multiple rows of devices arranged in columns; each row contains multiple transistor and resistor devices.

Abstract: An integrated biquadratic, continuous-time filter section includes a plurality of operational transconductance amplifiers (OTAs). Simutaneously changing a transconductance (GM) of each of the OTAs is provided by adjusting a differential voltage applied to a plurality of differential transistor pairs of each OTA. Each of the OTAs include a plurality of current sources and a common mode feedback circuit for controlling a common mode output voltage level. Changing the transconductance of the OTA is independent of the common mode voltage level control.

Abstract: An instruction pipeline includes a sequence of interconnected pipeline stages, each stage dedicated to one of several operations executed on data in a digital processing device. Control words govern execution of the operations as they progress through the pipeline. The pipeline stages, as well as the pipeline entry and exit, are interconnected in a manner that permits each control word to enter and exit the pipeline at any one of the stages, and to skip any stages in which the control word will not govern any operations on data. On occasion, this permits a control word to bypass another control word which originally preceded it in the pipeline, thus to reverse the order of the two control words. A mapping field in each control word predetermines its route through the instruction pipeline, one bit of the map field corresponding to each pipeline stage.

Abstract: A large communications network is linked to a primary terminal and a secondary terminal. The primary polls the secondary whenever it has data to send, and need not poll at any maximum fixed interval. The poll operation sends a sequence of data frames to the secondary, and causes the secondary to return to the primary a sequence of frames containing any data it may have ready. The secondary can only send data to the primary in response to a poll operation; however, the secondary has the capability of sending a uniquely identifiable frame on its own initiative whenever it has data ready to send and has not received a poll. This frame causes the primary to initiate a normal poll even though it has no data ready to send.

Abstract: An information processing network includes multiple processing devices, a main storage memory, and an interface coupling the processing devices to the main storage memory. All processing devices contend for control of the interface on an equal basis, subject to a dynamically shifting sequence of priority rankings, invoked to resolve contentions for the interface or for one of a plurality of hardware class locks. The class locks are uniquely associated with different capabilities or classes of data operations, which reduces the number of contentions and allows multiple operations to proceed simultaneously. Arbitration logic encompassing all of the processing devices is duplicated in each of the processing devices, and kept coherent through an interconnection of multiple data buses. One bus is associated with each processing device, receives the output of the associated processing device and provides the output to each of the other processing devices.

Abstract: A method and system in a data processing system having a display device for efficiently managing the display of an image. The image includes a number of segments, wherein only a portion of the segments may be simultaneously displayed within the display device at a selected resolution. The method and system of the present invention provides a substantially circular control icon having a defined periphery. One or more of the segments within the image may be associated with selected points along the defined periphery. A rotatable pointer element rotatable about a point within the substantially circular control icon is also provided. The portion of the segments displayed within the display device is selectively altered in response to a rotation of the rotatable pointer element. The display of the image also may be altered in response to movement of a slider or some other control element within the rotatable pointer element.

Abstract: An improved apparatus and method for isolating faults in a complex communications network such as a collision-detection network. A wrap plug connected to a communications adapter of a computer system simulates multiple functions of the network environment, rather than a single, hardwired function. A method performs a comprehensive yet convenient diagnostic test of multiple functions of the adapter while a terminal is disconnected from the network.

Abstract: A system for arbitration between competeting channels in, for example, a direct memory access (DMA) controller is described. The system arbitrates much more fairly than in the traditional `round robin` approach, especially when channel requests are not independent but instead are made and withdrawn simultaneously by groups of channels. A `turn-taken` latch is defined, and is consulted when a channel selection is made. This latch is set when a channel is serviced, and priority is given to requesting channel for which the latch is not set. When the latch is set for all of the requesting channels, an arbitrary winner is selected and the latch is reset for all except the winning channel.

Abstract: A method and system in a data processing system for managing a hierarchical error diagnostic system having a plurality of diagnostic modules for diagnosing a component failure within a target system having a predetermined group of components within each of a plurality of hierarchical levels. After the identification of selected hierarchical levels within the target system, and identification of the components within each hierarchical level, a first blackboard data storage area is initialized for utilization during a diagnostic session. Thereafter, a diagnostic analysis of a first predetermined group of components within a first selected hierarchical level is initiated. The diagnostic analysis utilizes the first blackboard data storage area and multiple diagnostic modules assigned to diagnose the components within the first selected hierarchical level. Upon conclusion of the diagnostic analysis, a diagnostic result is determined from selected information learned during the first diagnostic analysis.

Abstract: A stale packet removal apparatus and method are provided for a digital processing system of the type having multiple devices that communicate via a plurality of unidirectional rings. Each requesting device sets a traversal count value in a packet and then sends the packet. When the packet is received at an agent, the agent changes the traversal count value and sends the packet onto another of the unidirectional rings. When a device receives the packet, the device identifies the traversal count value and discards the packet responsive to a predefined traversal count value.