Abstract: In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting the performance (power) of each driver at each level. Where the capacitance of a net is too low to be compensated by a driver, a capacitive terminator is selectively added to that net.

Abstract: An optical fiber link card communication module, and process for fabricating the module, where the module provides a parallel electrical interface to the user, facilitates high speed serial transmission of data over an optical data link, and contains a plurality of converters for performing conversions between both electrical and optical signals. A preferred embodiment of the invention contemplates fabricating the optical communication module on a single multilayer card with all the transmitter electrical components being located on one side of the card, all receiver electrical components being located on the other side of the card, and the transmitter and receiver components being separated by shielding layers in the card. By using two transmitter/receiver pairs (with the transmitters and receivers being located on respective sides of the card) an embodiment of the invention provides for double full duplex communications.

Abstract: A WORM data storage medium includes primary and secondary data storage areas in which data and pointers to allocated but unwritten update areas are written. Original and updated data is written in a write sequence or chain of primary data areas separated by branched secondary data storage areas. The most recent updated data is found in a two level search of primary and then secondary data storage areas in order to save time by searching only those secondary areas where the most recent update exist.

Abstract: An optical fiber link card communication module, and process for fabricating the module, where the module provides a parallel electrical interface to the user, facilitates high speed serial transmission of data over an optical data link, and contains a plurality of converters for performing conversions between both electrical and optical signals. The module further includes edge mounted optical components having leads mounted on the surface of a card (as opposed to standard pin-in-hole type leads) to minimize lead capacitance and inductance from the optical components to the card electronics, on board card control means for the converters and safety shut down means on the same card as the electrical and optical components.

Abstract: A side-by-side double row of electronics packages plug into a common backplane. Cooling air flows in an (upside down) omega-shaped path turning into one row of packages, flowing through that row, turning through an air-moving device into a plenum chamber, then turning into the second row of packages, and out of the second row turning again to an outlet.

Abstract: On-line documentation for an application program resides in a number of help modules. A display file for the application program specifies command panels to be displayed. The command panel definition includes a mapping of screen areas to help modules as well as a designation of an index-sensitive search table. A user may access the on-line documentation either by pressing a function key for context-sensitive help (which displays the help module mapped to current cursor position) or by entering search words in an entry area for index-sensitive help. Index-sensitive help searches a table of synonyms, roots and topics which map to help modules, and lists the modules associated with the search word ordered by number of hits. Each command panel definition may specify a separate index-sensitive search table, permitting customization of the search to the application. The user then selects one or more of the listed modules for display.

Abstract: A floating-point arithmetic unit includes an exponent unit for biased exponents. Combinatorial bias-adjust logic removes the bias from one operand exponent before the two operand exponents are added together in adder for a multiply operation, and inserts a bias into one exponent before the exponents are subtracted by the adder for a divide operation.

Abstract: A word processor prepares a document having internal labels in the text. An application program contains a routine executable at various points for accessing the document and displaying its text at the label locations determined by the current position in the application.

Abstract: In a processor having a real address space larger than its virtual address space, all of the physical memory is addressed by using a separate prefix register associated with each of the address registers to hold both a high-order address portion and a control bit specifying whether the address is to be translated or used as a direct real address.

Abstract: A circuit for a partial-response, maximum likelihood (PRML) magnetic recording channel stretches and shrinks pulses in particular write-data sequences. The circuit maintains precise tracking in the delays among multiple signals by sending them through the same number of identical circuits on the same chip. An external digital code varies the amount of delay in a clock signal so as to stretch and shrink the data pulses by different amounts.

Abstract: A central processor holds a word-processing program and an entire document to be processed. A personal computer or intelligent terminal has an interactive display and holds code for some functions of the word processor, and stores individual pages of the document. As an operator performs editing tasks at the display, the personal computer performs locally those functions involving only the document page it holds. When additional document text is required to complete a function, the central processor performs the function on the full document. The central computer also performs all of certain other functions, regardless of where the data is stored.

Abstract: A differential analog input signal is level-shifted and converted to single-ended form. Its average value is compared to the midpoint of a set of reference voltages. A control signal proportional to the average value forces the average of the single-ended signal toward the midpoint voltage. The single-ended signal is converted to uncoded digital form by a parallel comparator bank, and is then converted to coded digital form.

Abstract: A performance-sensing element (PSE) circuit detects the actual speed of other circuits on the same chip by launching a pulse into a tapped cascade of circuits on the chip, then detecting how far the pulse has progressed after a known interval. Control signals indicating circuit speed can stabilize parameters of the other circuits, such as rate of change of current (di/dt) in driver circuits, absolute delay of clock signals from one chip to another, and relative delay of multiple clock signals within the chip.